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12

/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Drenesas,rpc-if.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/renesas,rpc-if.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas Reduced Pin Count Interface (RPC-IF)
10 - Sergei Shtylyov <sergei.shtylyov@gmail.com>
13 Renesas RPC-IF allows a SPI flash or HyperFlash connected to the SoC to
16 The flash chip itself should be represented by a subnode of the RPC-IF node.
19 - if it contains "jedec,spi-nor", then SPI is used;
20 - if it contains "cfi-flash", then HyperFlash is used.
[all …]
/openbmc/linux/drivers/clk/renesas/
H A Drcar-cpg-lib.c1 // SPDX-License-Identifier: GPL-2.0
3 * R-Car Gen3 Clock Pulse Generator Library
5 * Copyright (C) 2015-2018 Glider bvba
8 * Based on clk-rcar-gen3.c
14 #include <linux/clk-provider.h>
23 #include "rcar-cpg-lib.h"
48 csn->saved = readl(csn->reg); in cpg_simple_notifier_call()
52 writel(csn->saved, csn->reg); in cpg_simple_notifier_call()
61 csn->nb.notifier_call = cpg_simple_notifier_call; in cpg_simple_notifier_register()
62 raw_notifier_chain_register(notifiers, &csn->nb); in cpg_simple_notifier_register()
[all …]
H A Dr8a77970-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2017-2018 Cogent Embedded Inc.
7 * Based on r8a7795-cpg-mssr.c
12 #include <linux/clk-provider.h>
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
95 DEF_FIXED("rpc", R8A77970_CLK_RPC, CLK_PLL1_DIV2, 5, 1),
126 DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),
[all …]
H A Dr8a77995-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on r8a7795-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
112 DEF_BASE("rpc", R8A77995_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
136 DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
137 DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
138 DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
[all …]
H A Dr8a7795-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2018-2019 Renesas Electronics Corp.
8 * Based on clk-rcar-gen3.c
16 #include <linux/soc/renesas/rcar-rst.h>
19 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen3-cpg.h"
113 DEF_BASE("rpc", R8A7795_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
133 DEF_MOD("fdp1-1", 118, R8A7795_CLK_S0D1),
134 DEF_MOD("fdp1-0", 119, R8A7795_CLK_S0D1),
[all …]
H A Dr8a77980-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
8 * Based on r8a7795-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
19 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
21 #include "renesas-cpg-mssr.h"
22 #include "rcar-gen3-cpg.h"
100 DEF_BASE("rpc", R8A77980_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
129 DEF_MOD("sys-dmac2", 217, R8A77980_CLK_S0D3),
130 DEF_MOD("sys-dmac1", 218, R8A77980_CLK_S0D3),
139 DEF_MOD("intc-ex", 407, R8A77980_CLK_CP),
[all …]
H A Dr8a774c0-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
7 * Based on r8a77990-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
106 DEF_BASE("rpc", R8A774C0_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
149 DEF_MOD("sys-dmac2", 217, R8A774C0_CLK_S3D1),
150 DEF_MOD("sys-dmac1", 218, R8A774C0_CLK_S3D1),
151 DEF_MOD("sys-dmac0", 219, R8A774C0_CLK_S3D1),
[all …]
H A Dr8a77990-cpg-mssr.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
7 * Based on r8a7795-cpg-mssr.c
16 #include <linux/soc/renesas/rcar-rst.h>
18 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
20 #include "renesas-cpg-mssr.h"
21 #include "rcar-gen3-cpg.h"
113 DEF_BASE("rpc", R8A77990_CLK_RPC, CLK_TYPE_GEN3_RPC, CLK_RPCSRC),
150 DEF_MOD("sys-dmac2", 217, R8A77990_CLK_S3D1),
151 DEF_MOD("sys-dmac1", 218, R8A77990_CLK_S3D1),
[all …]
/openbmc/u-boot/drivers/mtd/
H A DKconfig30 for probing the capabilities of flash devices. If you wish to
31 support any device that is CFI-compliant, you need to enable this
41 for probing the capabilities of flash devices. If you wish to
42 support any device that is CFI-compliant, you need to enable this
64 If defined, hardware flash sectors protection is used
65 instead of U-Boot software protection.
71 Define if the flash driver uses extra elements in the
87 This enables access to Microchip PIC32 internal non-CFI flash
88 chips through PIC32 Non-Volatile-Memory Controller.
91 bool "Renesas RCar Gen3 RPC Hyperflash driver"
[all …]
H A Drenesas_rpc_hf.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RCar Gen3 RPC Hyperflash driver
171 if (ret) in rpc_hf_mode()
184 if (man) in rpc_hf_mode()
211 if (ret) in rpc_hf_xfer()
226 if (write) { in rpc_hf_xfer()
229 if (size == RPC_HF_SIZE_64BIT) in rpc_hf_xfer()
245 if (ret) in rpc_hf_xfer()
248 if (size == RPC_HF_SIZE_64BIT) in rpc_hf_xfer()
262 if (ret) in rpc_hf_write_cmd()
[all …]
/openbmc/linux/arch/arm64/boot/dts/renesas/
H A Dr8a77970.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car V3M (R8A77970) SoC
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
9 #include <dt-bindings/clock/r8a77970-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/interrupt-controller/irq.h>
12 #include <dt-bindings/power/r8a77970-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
19 /* External CAN clock - to be overridden by boards that provide it */
[all …]
H A Dr8a77995.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car D3 (R8A77995) SoC
9 #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/power/r8a77995-sysc.h>
15 #address-cells = <2>;
16 #size-cells = <2>;
24 compatible = "fixed-clock";
25 #clock-cells = <0>;
26 clock-frequency = <0>;
[all …]
H A Dr8a77980.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car V3H (R8A77980) SoC
9 #include <dt-bindings/clock/r8a77980-cpg-mssr.h>
10 #include <dt-bindings/interrupt-controller/irq.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/r8a77980-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
19 /* External CAN clock - to be overridden by boards that provide it */
21 compatible = "fixed-clock";
[all …]
H A Dr8a774c0.dtsi1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a774c0-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a774c0-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
25 clock-frequency = <0>;
[all …]
H A Dr8a77990.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car E3 (R8A77990) SoC
5 * Copyright (C) 2018-2019 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a77990-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a77990-sysc.h>
14 #address-cells = <2>;
15 #size-cells = <2>;
23 compatible = "fixed-clock";
24 #clock-cells = <0>;
[all …]
H A Dr8a77965.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M3-N (R8A77965) SoC
11 #include <dt-bindings/clock/r8a77965-cpg-mssr.h>
12 #include <dt-bindings/interrupt-controller/arm-gic.h>
13 #include <dt-bindings/power/r8a77965-sysc.h>
21 #address-cells = <2>;
22 #size-cells = <2>;
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <0>;
[all …]
H A Dr8a774b1.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
11 #include <dt-bindings/power/r8a774b1-sysc.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <0>;
[all …]
H A Dr8a774a1.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a774a1-cpg-mssr.h>
11 #include <dt-bindings/power/r8a774a1-sysc.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <0>;
[all …]
H A Dr8a77961.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M3-W+ (R8A77961) SoC
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a77961-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a77961-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
[all …]
H A Dr8a77960.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car M3-W (R8A77960) SoC
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
8 #include <dt-bindings/clock/r8a7796-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a7796-sysc.h>
16 #address-cells = <2>;
17 #size-cells = <2>;
25 compatible = "fixed-clock";
26 #clock-cells = <0>;
[all …]
H A Dr8a774e1.dtsi1 // SPDX-License-Identifier: GPL-2.0
8 #include <dt-bindings/interrupt-controller/irq.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/clock/r8a774e1-cpg-mssr.h>
11 #include <dt-bindings/power/r8a774e1-sysc.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
26 compatible = "fixed-clock";
27 #clock-cells = <0>;
28 clock-frequency = <0>;
[all …]
H A Dr8a77951.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car H3 (R8A77951) SoC
8 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
9 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #include <dt-bindings/power/r8a7795-sysc.h>
21 #address-cells = <2>;
22 #size-cells = <2>;
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <0>;
[all …]
/openbmc/u-boot/arch/arm/mach-rmobile/
H A Dmemmap-gen3.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Renesas RCar Gen3 memory map tables
61 /* Create map for RPC access */ in enable_caches()
72 start = gd->bd->bi_dram[bank].start; in enable_caches()
73 size = gd->bd->bi_dram[bank].size; in enable_caches()
76 if (!size) in enable_caches()
80 if (start >> 32ULL) in enable_caches()
84 if (start == 0x48000000) { in enable_caches()
116 start = gd->bd->bi_dram[bank].start; in enable_caches()
117 size = gd->bd->bi_dram[bank].size; in enable_caches()
[all …]
/openbmc/linux/drivers/memory/
H A Drenesas-rpc-if.c1 // SPDX-License-Identifier: GPL-2.0
3 * Renesas RPC-IF core driver
5 * Copyright (C) 2018-2019 Renesas Solutions Corp.
7 * Copyright (C) 2019-2020 Cogent Embedded, Inc.
19 #include <memory/renesas-rpc-if.h>
43 #define RPCIF_DRCR_RBURST(v) ((((v) - 1) & 0x1F) << 16)
111 #define RPCIF_DMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
120 #define RPCIF_SMDMCR_DMCYC(v) ((((v) - 1) & 0x1F) << 0)
128 #define RPCIF_PHYADD 0x0070 /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
129 #define RPCIF_PHYWR 0x0074 /* R/W available on R-Car E3/D3/V3M and RZ/G2{E,L} */
[all …]
/openbmc/u-boot/drivers/clk/renesas/
H A Dclk-rcar-gen3.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Renesas RCar Gen3 CPG MSSR driver
14 #include <clk-uclass.h>
20 #include <dt-bindings/clock/renesas-cpg-mssr.h>
22 #include "renesas-cpg-mssr.h"
23 #include "rcar-gen3-cpg.h"
62 *-------------------------------------------------------------------
94 if (!renesas_clk_is_mod(clk)) { in gen3_clk_get_parent()
96 if (ret) in gen3_clk_get_parent()
99 if (core->type == CLK_TYPE_GEN3_PE) { in gen3_clk_get_parent()
[all …]

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