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/openbmc/smbios-mdr/include/
H A Dcpu.hpp8 // http://www.apache.org/licenses/LICENSE-2.0
80 {0x1b, "K6-2"},
81 {0x1c, "K6-3"},
84 {0x1f, "K6-2+"},
93 {0x28, "Intel Core Duo processor"},
94 {0x29, "Intel Core Duo mobile processor"},
95 {0x2a, "Intel Core Solo mobile processor"},
97 {0x2c, "Intel Core M processor"},
98 {0x2d, "Intel Core m3 processor"},
99 {0x2e, "Intel Core m
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/openbmc/linux/Documentation/devicetree/bindings/mips/loongson/
H A Ddevices.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jiaxun Yang <jiaxun.yang@flygoat.com>
20 - description: Classic Loongson64 Quad Core + LS7A
22 - const: loongson,loongson64c-4core-ls7a
24 - description: Classic Loongson64 Quad Core + RS780E
26 - const: loongson,loongson64c-4core-rs780e
28 - description: Classic Loongson64 Octa Core + RS780E
30 - const: loongson,loongson64c-8core-rs780e
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/openbmc/u-boot/drivers/spi/
H A DKconfig16 typically use driver-private data instead of extending the
24 by providing an high-level interface to send memory-like commands.
33 IP core. Please find details on the "Embedded Peripherals IP
56 this Andestech IP core.
65 please refer to doc/device-tree-bindings/spi/spi-ath79.txt.
81 SPI core.
94 Enable the Broadcom set-top box SPI driver. This driver can
96 Broadcom SPI core.
101 Enable the Cadence Quad-SPI (QSPI) driver. This driver can be
103 Cadence IP core.
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/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Dactions.yaml1 # SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andreas Färber <afaerber@suse.de>
11 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
18 # The Actions Semi S500 is a quad-core ARM Cortex-A9 SoC.
19 - items:
20 - enum:
21 - allo,sparky # Allo.com Sparky
22 - cubietech,cubieboard6 # Cubietech CubieBoard6
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H A Dfsl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <shawnguo@kernel.org>
11 - Li Yang <leoyang.li@nxp.com>
18 - description: i.MX1 based Boards
20 - enum:
21 - armadeus,imx1-apf9328
22 - fsl,imx1ads
23 - const: fsl,imx1
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/openbmc/u-boot/arch/arm/mach-rockchip/
H A DKconfig11 The Rockchip RK3036 is a ARM-based SoC with a dual-core Cortex-A7
12 including NEON and GPU, Mali-400 graphics, several DDR3 options
20 The Rockchip RK3128 is a ARM-based SoC with a quad-core Cortex-A7
21 including NEON and GPU, Mali-400 graphics, several DDR3 options
41 The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9
42 including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two
55 The Rockchip RK3229 is a ARM-based SoC with a dual-core Cortex-A7
56 including NEON and GPU, Mali-400 graphics, several DDR3 options
69 The Rockchip RK3288 is a ARM-based SoC with a quad-core Cortex-A17
70 including NEON and GPU, 1MB L2 cache, Mali-T7 graphics, two
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/openbmc/linux/arch/arm64/crypto/
H A Dsha512-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions
37 * The SHA-512 round constants
42 .quad 0x428a2f98d728ae22, 0x7137449123ef65cd
43 .quad 0xb5c0fbcfec4d3b2f, 0xe9b5dba58189dbbc
44 .quad 0x3956c25bf348b538, 0x59f111f1b605d019
45 .quad 0x923f82a4af194f9b, 0xab1c5ed5da6d8118
46 .quad 0xd807aa98a3030242, 0x12835b0145706fbe
47 .quad 0x243185be4ee4b28c, 0x550c7dc3d5ffb4e2
48 .quad 0x72be5d74f27b896f, 0x80deb1fe3b1696b1
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H A Dsha3-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha3-ce-core.S - core SHA-3 transform using v8.2 Crypto Extensions
46 ld1 { v0.1d- v3.1d}, [x0]
47 ld1 { v4.1d- v7.1d}, [x8], #32
48 ld1 { v8.1d-v11.1d}, [x8], #32
49 ld1 {v12.1d-v15.1d}, [x8], #32
50 ld1 {v16.1d-v19.1d}, [x8], #32
51 ld1 {v20.1d-v23.1d}, [x8], #32
59 ld1 {v25.8b-v28.8b}, [x1], #32
60 ld1 {v29.8b-v31.8b}, [x1], #24
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/openbmc/linux/Documentation/devicetree/bindings/arm/marvell/
H A Darmada-7k-8k.yaml1 # SPDX-License-Identifier: (GPL-2.0+ OR X11)
3 ---
4 $id: http://devicetree.org/schemas/arm/marvell/armada-7k-8k.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Gregory CLEMENT <gregory.clement@bootlin.com>
18 - description: Armada 7020 SoC
20 - const: marvell,armada7020
21 - const: marvell,armada-ap806-dual
22 - const: marvell,armada-ap806
24 - description: Armada 7040 SoC
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/openbmc/linux/Documentation/arch/arm/
H A Dmarvell.rst13 ------------
16 - 88F5082
17 - 88F5181 a.k.a Orion-1
18 - 88F5181L a.k.a Orion-VoIP
19 - 88F5182 a.k.a Orion-NAS
21 …- Datasheet: https://web.archive.org/web/20210124231420/http://csclub.uwaterloo.ca/~board/ts7800/M…
22 …- Programmer's User Guide: https://web.archive.org/web/20210124231536/http://csclub.uwaterloo.ca/~…
23 …- User Manual: https://web.archive.org/web/20210124231631/http://csclub.uwaterloo.ca/~board/ts7800…
24 …- Functional Errata: https://web.archive.org/web/20210704165540/https://www.digriz.org.uk/ts78xx/8…
25 - 88F5281 a.k.a Orion-2
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/openbmc/linux/Documentation/hwmon/
H A Dk10temp.rst8 Socket F: Quad-Core/Six-Core/Embedded Opteron (but see below)
10 Socket AM2+: Quad-Core Opteron, Phenom (II) X3/X4, Athlon X2 (but see below)
12 Socket AM3: Quad-Core Opteron, Athlon/Phenom II X2/X3/X4, Sempron II
20 * AMD Family 12h processors: "Llano" (E2/A4/A6/A8-Series)
22 * AMD Family 14h processors: "Brazos" (C/E/G/Z-Series)
24 * AMD Family 15h processors: "Bulldozer" (FX-Series), "Trinity", "Kaveri",
53 BIOS and Kernel Developer's Guide (BKDG) for AMD Family 14h Models 00h-0Fh Processors:
69 Revision Guide for AMD Family 14h Models 00h-0Fh Processors:
88 -----------
109 control cooling systems. Tctl is a non-physical temperature on an
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H A Dcoretemp.rst5 * All Intel Core family
11 - 0xe (Pentium M DC), 0xf (Core 2 DC 65nm),
12 - 0x16 (Core 2 SC 65nm), 0x17 (Penryn 45nm),
13 - 0x1a (Nehalem), 0x1c (Atom), 0x1e (Lynnfield),
14 - 0x26 (Tunnel Creek Atom), 0x27 (Medfield Atom),
15 - 0x36 (Cedar Trail Atom)
19 Intel 64 and IA-32 Architectures Software Developer's Manual
27 -----------
30 inside Intel CPUs. This driver can read both the per-core and per-package
31 temperature using the appropriate sensors. The per-package sensor is new;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dqcom,spi-qcom-qspi.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/qcom,spi-qcom-qspi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Quad Serial Peripheral Interface (QSPI)
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
13 dual, or quad wire transmission modes for read/write access to slaves such
17 - $ref: /schemas/spi/spi-controller.yaml#
22 - enum:
23 - qcom,sc7180-qspi
[all …]
H A Dnvidia,tegra210-quad-peripheral-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/nvidia,tegra210-quad-peripheral-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Peripheral properties for Tegra Quad SPI Controller
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
14 nvidia,tx-clk-tap-delay:
23 nvidia,rx-clk-tap-delay:
/openbmc/linux/drivers/spi/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
13 dynamic device discovery; some are even write-only or read-only.
17 chips, analog to digital (and d-to-a) converters, and more.
44 If your system has an master-capable SPI controller (which
56 by providing a high-level interface to send memory-like commands.
68 tristate "Altera SPI Controller core code" if COMPILE_TEST
71 "The core code for the Altera SPI Controller"
139 tristate "Atmel Quad SPI Controller"
143 This enables support for the Quad SPI controller in master mode.
145 supports spi-mem interface.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,admv1013.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
21 - adi,admv1013
26 spi-max-frequency:
34 clock-names:
36 - const: lo_in
38 vcm-supply:
42 vcc-drv-supply:
[all …]
H A Dadi,admv1014.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
21 - adi,admv1014
26 spi-max-frequency:
32 clock-names:
34 - const: lo_in
38 vcm-supply:
40 Common-mode voltage regulator.
[all …]
/openbmc/u-boot/board/intel/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0+
15 Intel quad-core Atom Processor E3800 with dual-channel DDR3L SODIMM
23 mini-ITX form factor containing the Intel Braswell SoC, which has
24 a 64-bit quad-core, single-thread, Intel Atom processor, along with
25 serial console, 10/100/1000 Ethernet, SD-Card, USB 2/3, SATA, PCIe,
48 This is the Intel Edison Compute Module. It contains a dual core Intel
50 eMMC flash on board, Wi-Fi, Bluetooth 4 and USB controllers.
56 Arduino-certified development and prototyping boards based on Intel
57 architecture. It includes an Intel Quark SoC X1000 processor, a 32-bit
58 single-core, single-thread, Intel Pentium processor instrunction set
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/openbmc/linux/Documentation/infiniband/
H A Dopa_vnic.rst2 Intel Omni-Path (OPA) Virtual Network Interface Controller (VNIC)
5 Intel Omni-Path (OPA) Virtual Network Interface Controller (VNIC) feature
6 supports Ethernet functionality over Omni-Path fabric by encapsulating
11 The patterns of exchanges of Omni-Path encapsulated Ethernet packets
12 involves one or more virtual Ethernet switches overlaid on the Omni-Path
13 fabric topology. A subset of HFI nodes on the Omni-Path fabric are
26 +-------------------+
30 +-------------------+
35 +-----------------------------+ +------------------------------+
37 | +---------+ +---------+ | | +---------+ +---------+ |
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/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dadi,adau1977.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Analog Devices ADAU1977/ADAU1978/ADAU1979 Quad ADC with Diagnostics
10 - Lars-Peter Clausen <lars@metafoo.de>
11 - Bogdan Togorean <bogdan.togorean@analog.com>
14 Analog Devices ADAU1977 and similar quad ADC with Diagnostics
15 https://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1977.pdf
16 https://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1978.pdf
17 https://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1979.pdf
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/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmicrochip,lan966x-switch.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Horatiu Vultur <horatiu.vultur@microchip.com>
13 The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
14 two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
15 it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
16 2 Quad-SGMII/Quad-USGMII interfaces.
20 pattern: "^switch@[0-9a-f]+$"
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/openbmc/u-boot/arch/arm/cpu/armv8/
H A Dstart.S1 /* SPDX-License-Identifier: GPL-2.0+ */
7 #include <asm-offsets.h>
22 #include <asm/boot0-linux-kernel-header.h>
25 * Various SoCs need something special and SoC-specific up front in
38 .quad CONFIG_SYS_TEXT_BASE
45 .quad _end - _start
49 .quad __bss_start - _start
53 .quad __bss_end - _start
63 * Fix .rela.dyn relocations. This allows U-Boot to be loaded to and
67 adr x0, _start /* x0 <- Runtime value of _start */
[all …]
/openbmc/linux/arch/x86/events/intel/
H A Duncore_snb.c1 // SPDX-License-Identifier: GPL-2.0
161 #define SNB_UNC_GLOBAL_CTL_CORE_ALL ((1 << 4) - 1)
180 #define NHM_UNC_GLOBAL_CTL_EN_PC_ALL ((1ULL << 8) - 1)
189 #define SKL_UNC_GLOBAL_CTL_CORE_ALL ((1 << 5) - 1)
247 DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
248 DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
249 DEFINE_UNCORE_FORMAT_ATTR(chmask, chmask, "config:8-11");
252 DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28");
253 DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31");
254 DEFINE_UNCORE_FORMAT_ATTR(threshold, threshold, "config:24-29");
[all …]
/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc13 ---------
14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
20 - Four 64-bit ARM Cortex-A53 CPUs
21 - 1 MB unified L2 Cache
22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
24 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
26 - Packet parsing, classification, and distribution (FMan)
27 - Queue management for scheduling, packet sequencing, and congestion
29 - Hardware buffer management for buffer allocation and de-allocation (BMan)
30 - Cryptography acceleration (SEC)
[all …]
/openbmc/qemu/hw/ppc/
H A Dpnv_core.c2 * QEMU PowerPC PowerNV CPU Core model
32 #include "hw/qdev-properties.h"
38 int len = strlen(core_type) - strlen(PNV_CORE_TYPE_SUFFIX); in pnv_core_cpu_typename()
48 CPUPPCState *env = &cpu->env; in pnv_core_cpu_reset()
49 PnvChipClass *pcc = PNV_CHIP_GET_CLASS(pc->chip); in pnv_core_cpu_reset()
57 env->gpr[3] = PNV_FDT_ADDR; in pnv_core_cpu_reset()
58 env->nip = 0x10; in pnv_core_cpu_reset()
59 env->msr |= MSR_HVB; /* Hypervisor mode */ in pnv_core_cpu_reset()
60 env->spr[SPR_HRMOR] = pc->hrmor; in pnv_core_cpu_reset()
61 if (pc->big_core) { in pnv_core_cpu_reset()
[all …]

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