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/openbmc/u-boot/arch/arm/mach-davinci/include/mach/
H A Dpinmux_defs.h1 /* SPDX-License-Identifier: GPL-2.0+ */
14 /* SPI0 pin muxer settings */
19 /* SPI1 pin muxer settings */
23 /* UART pin muxer settings */
30 /* EMAC pin muxer settings*/
36 /* I2C pin muxer settings */
40 /* EMIFA pin muxer settings */
49 /* USB pin mux setting */
52 /* MMC pin muxer settings */
/openbmc/u-boot/board/sunxi/
H A Dgmac.c11 int pin; local
17 setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_RESET_OFFSET_GMAC);
18 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_GMAC);
20 setbits_le32(&ccm->ahb_gate1, 0x1 << AHB_GATE_OFFSET_GMAC);
25 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII |
27 setbits_le32(&ccm->gmac_clk_cfg,
30 setbits_le32(&ccm->gmac_clk_cfg, CCM_GMAC_CTRL_TX_CLK_SRC_MII |
35 /* Configure pin mux settings for GMAC */
37 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(17); pin++) {
39 for (pin = SUNXI_GPA(0); pin <= SUNXI_GPA(16); pin++) {
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,imx-pinctrl.txt7 different PAD settings (like pull up, keeper, etc) the IOMUXC controls
8 also the PAD settings parameters.
10 Please refer to pinctrl-bindings.txt in this directory for details of the
12 phrase "pin configuration node".
14 Freescale IMX pin configuration node is a node of a group of pins which can be
17 mode) this pin can work on and the 'config' configures various pad settings
18 such as pull-up, open drain, drive strength, etc.
21 - compatible: "fsl,<soc>-iomuxc"
22 Please refer to each fsl,<soc>-pinctrl.txt binding doc for supported SoCs.
24 Required properties for pin configuration node:
[all …]
H A Datmel,at91-pinctrl.txt7 different PAD settings (like pull up, keeper, etc) the controller controls
8 also the PAD settings parameters.
10 Please refer to pinctrl-bindings.txt in this directory for details of the
12 phrase "pin configuration node".
14 Atmel AT91 pin configuration node is a node of a group of pins which can be
16 of the pins in that group. The 'pins' selects the function mode(also named pin
17 mode) this pin can work on and the 'config' configures various pad settings
18 such as pull-up, multi drive, etc.
21 - compatible: "atmel,at91rm9200-pinctrl" or "atmel,at91sam9x5-pinctrl"
22 or "atmel,sama5d3-pinctrl" or "microchip,sam9x60-pinctrl"
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H A Dpinmux-node.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinmux-node.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic Pin Multiplexing Node
10 - Linus Walleij <linus.walleij@linaro.org>
13 The contents of the pin configuration child nodes are defined by the binding
14 for the individual pin controller device. The pin configuration nodes need not
15 be direct children of the pin controller device; they may be grandchildren,
18 the binding for the individual pin controller device.
[all …]
H A Dfsl,imx7d-pinctrl.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/fsl,imx7d-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dong Aisheng <aisheng.dong@nxp.com>
13 Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
19 - enum:
20 - fsl,imx7d-iomuxc
21 - fsl,imx7d-iomuxc-lpsr
26 fsl,input-sel:
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H A Dbrcm,nsp-gpio.txt4 - compatible:
5 Must be "brcm,nsp-gpio-a"
7 - reg:
11 - #gpio-cells:
12 Must be two. The first cell is the GPIO pin number (within the
13 controller's pin space) and the second cell is used for the following:
16 - gpio-controller:
19 - ngpios:
23 - interrupts:
26 - interrupt-controller:
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/openbmc/linux/drivers/pinctrl/mvebu/
H A Dpinctrl-mvebu.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
13 * struct mvebu_mpp_ctrl_data - private data for the mpp ctrl operations
29 * struct mvebu_mpp_ctrl - describe a mpp control
31 * @pid: first pin id handled by this control
38 * A mpp_ctrl describes a muxable unit, e.g. pin, group of pins, or
40 * between two or more different settings, e.g. assign mpp pin 13 to
45 * to allow pin settings with varying gpio pins.
62 * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
64 * @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
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/openbmc/linux/Documentation/arch/arm/pxa/
H A Dmfp.rst7 MFP stands for Multi-Function Pin, which is the pin-mux logic on PXA3xx and
14 Unlike the GPIO alternate function settings on PXA25x and PXA27x, a new MFP
15 mechanism is introduced from PXA3xx to completely move the pin-mux functions
16 out of the GPIO controller. In addition to pin-mux configurations, the MFP
17 also controls the low power state, driving strength, pull-up/down and event
18 detection of each pin. Below is a diagram of internal connections between
21 +--------+
22 | |--(GPIO19)--+
24 | |--(GPIO...) |
25 +--------+ |
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/openbmc/linux/drivers/pinctrl/
H A Dcore.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Core private header for the pin control subsystem
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
14 #include <linux/radix-tree.h>
30 * struct pinctrl_dev - pin control class device
31 * @node: node to include this pin controller in the global pin controller list
32 * @desc: the pin controller descriptor supplied when initializing this pin
34 * @pin_desc_tree: each pin descriptor for this pin controller is stored in
36 * @pin_group_tree: optionally each pin group can be stored in this radix tree
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H A Dpinctrl-single.c2 * Generic device tree based pinctrl driver for one register per pin
25 #include <linux/pinctrl/pinconf-generic.h>
30 #include <linux/platform_data/pinctrl-single.h>
37 #define DRIVER_NAME "pinctrl-single"
41 * struct pcs_func_vals - mux function register offset and value pair
53 * struct pcs_conf_vals - pinconf parameter, pinconf register offset
70 * struct pcs_conf_type - pinconf property name, pinconf param pair
80 * struct pcs_function - pinctrl function
86 * @conf: array of pin configurations
87 * @nconfs: number of pin configurations available
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H A Dcore.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Core driver for the pin control subsystem
5 * Copyright (C) 2011-2012 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
51 /* Global list of pin control devices (struct pinctrl_dev) */
54 /* List of pin controller handles (struct pinctrl) */
62 * pinctrl_provide_dummies() - indicate if pinctrl provides dummy state support
77 return pctldev->desc->name; in pinctrl_dev_get_name()
83 return dev_name(pctldev->dev); in pinctrl_dev_get_devname()
89 return pctldev->driver_data; in pinctrl_dev_get_drvdata()
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H A Dpinctrl-axp209.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2016 Maxime Ripard <maxime.ripard@free-electrons.com>
6 * Copyright (C) 2017 Quentin Schulz <quentin.schulz@free-electrons.com>
23 #include <linux/pinctrl/pinconf-generic.h>
52 /* Stores the pins supporting LDO function. Bit offset is pin number. */
54 /* Stores the pins supporting ADC function. Bit offset is pin number. */
124 return -EINVAL; in axp20x_gpio_get_reg()
129 return pinctrl_gpio_direction_input(chip->base + offset); in axp20x_gpio_input()
138 /* AXP209 has GPIO3 status sharing the settings register */ in axp20x_gpio_get()
140 ret = regmap_read(pctl->regmap, AXP20X_GPIO3_CTRL, &val); in axp20x_gpio_get()
[all …]
H A Dpinconf.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Core driver for the pin config portions of the pin control subsystem
5 * Copyright (C) 2011 ST-Ericsson SA
6 * Written on behalf of Linaro for ST-Ericsson
27 const struct pinconf_ops *ops = pctldev->desc->confops; in pinconf_check_ops()
30 if (!ops->pin_config_set && !ops->pin_config_group_set) { in pinconf_check_ops()
31 dev_err(pctldev->dev, in pinconf_check_ops()
33 return -EINVAL; in pinconf_check_ops()
40 if (!map->data.configs.group_or_pin) { in pinconf_validate_map()
41 pr_err("failed to register map %s (%d): no group/pin given\n", in pinconf_validate_map()
[all …]
/openbmc/linux/drivers/staging/media/atomisp/pci/
H A Datomisp_csi2_bridge.c1 // SPDX-License-Identifier: GPL-2.0
8 * Based on drivers/media/pci/intel/ipu3/cio2-bridge.c written by:
18 #include <media/ipu-bridge.h>
19 #include <media/v4l2-fwnode.h>
28 * 79234640-9e10-4fea-a5c1-b5aa8b19756f
52 * 822ace8f-2814-4174-a56b-5f029fe079ee
61 * dc2f6c4f-045b-4f1d-97b9-882a6860a4be
63 * forming a key, value pair for settings like e.g. "CsiLanes" = "1".
70 * 75c9a639-5c8a-4a00-9f48-a9c3b5da789f
94 * Once all sensors are moved to v4l2-async probing atomisp_gmin_platform.c can
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/openbmc/linux/include/linux/ssb/
H A Dssb_regs.h1 /* SPDX-License-Identifier: GPL-2.0 */
33 #define SSB_MAX_NR_CORES ((SSB_ENUM_LIMIT - SSB_ENUM_BASE) / SSB_CORE_SIZE)
108 #define SSB_TMSHIGH_SERR 0x00000001 /* S-error */
168 * in two-byte quantities.
192 #define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
202 #define SSB_SPROM1_BINF_ANTBG 0x3000 /* Available B-PHY and G-PHY antennas */
204 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
210 #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
211 #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
214 #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
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/openbmc/u-boot/arch/arm/mach-davinci/
H A Dda850_pinmux.c1 // SPDX-License-Identifier: GPL-2.0+
13 /* SPI pin muxer settings */
34 /* UART pin muxer settings */
60 /* EMAC pin muxer settings*/
95 /* I2C pin muxer settings */
106 /* EMIFA pin muxer settings */
134 /* NOR pin muxer settings */
181 /* MMC0 pin muxer settings */
189 /* DA850 supports only 4-bit mode, remaining pins are not configured */
/openbmc/u-boot/arch/x86/cpu/broadwell/
H A Dpinctrl_broadwell.c1 // SPDX-License-Identifier: GPL-2.0+
17 #include <dt-bindings/gpio/x86-gpio.h>
19 #include <dm/uclass-internal.h>
49 const void *blob = gd->fdt_blob; in broadwell_pinctrl_read_configs()
62 return -ENOSPC; in broadwell_pinctrl_read_configs()
66 conf->node = node; in broadwell_pinctrl_read_configs()
67 conf->phandle = phandle; in broadwell_pinctrl_read_configs()
68 conf->mode_gpio = fdtdec_get_bool(blob, node, "mode-gpio"); in broadwell_pinctrl_read_configs()
69 if (fdtdec_get_int(blob, node, "direction", -1) == PIN_INPUT) in broadwell_pinctrl_read_configs()
70 conf->dir_input = true; in broadwell_pinctrl_read_configs()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dpinmux.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * (C) Copyright 2010-2014
14 /* The pullup/pulldown state of a pin group */
21 /* Defines whether a pin group is tristated or in normal operation */
76 /* Defines a pin group cfg's low-power mode select */
82 PMUX_LPMD_NONE = -1,
87 /* Defines whether a pin group cfg's schmidt is enabled or not */
91 PMUX_SCHMT_NONE = -1,
96 /* Defines whether a pin group cfg's high-speed mode is enabled or not */
100 PMUX_HSM_NONE = -1,
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/openbmc/linux/Documentation/driver-api/
H A Dpin-control.rst2 PINCTRL (PIN CONTROL) subsystem
5 This document outlines the pin control subsystem in Linux
9 - Enumerating and naming controllable pins
11 - Multiplexing of pins, pads, fingers (etc) see below for details
13 - Configuration of pins, pads, fingers (etc), such as software-controlled
14 biasing and driving mode specific pins, such as pull-up, pull-down, open drain,
17 Top-level interface
22 - A PIN CONTROLLER is a piece of hardware, usually a set of registers, that
26 - PINS are equal to pads, fingers, balls or whatever packaging input or
28 in the range 0..maxpin. This numberspace is local to each PIN CONTROLLER, so
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/openbmc/u-boot/board/BuR/common/
H A Dcommon.c1 // SPDX-License-Identifier: GPL-2.0+
8 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
28 #include "../../../drivers/video/am335x-fb.h"
32 /* --------------------------------------------------------------------------*/
57 case 0: /* PMIC LED-Driver */ in lcdbacklight()
70 timerhw->tiocp_cfg = TCFG_RESET; in lcdbacklight()
72 while (timerhw->tiocp_cfg & TCFG_RESET) in lcdbacklight()
74 tmp = ~0UL-(V_OSCK/pwmfrq); /* bottom value */ in lcdbacklight()
75 timerhw->tldr = tmp; in lcdbacklight()
76 timerhw->tcrr = tmp; in lcdbacklight()
[all …]
/openbmc/u-boot/board/sbc8641d/
H A DREADME7 -----------------------------
9 1. Building U-Boot
10 ------------------
19 2. Switch and Jumper Settings
20 -----------------------------
22 the board documentation for details. Some settings control CPU voltages
23 and settings may change with board revisions.
26 --------------------
30 4. Reflashing U-Boot
31 --------------------
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/openbmc/openbmc/meta-openembedded/meta-oe/recipes-connectivity/gammu/gammu/
H A Dgammu-smsdrc1 # This is a sample Gammu SMSD configuration file. It's required for gammu-smsd,
2 # see gammu-smsdrc(5) for documentation.
30 # General SMSD settings, see gammu-smsdrc(5) for detailed description.
34 # PIN for SIM card
35 PIN = 0000
44 # Commication frequency settings
49 # Phone communication settings
/openbmc/linux/Documentation/devicetree/bindings/display/tilcdc/
H A Dpanel.txt1 Device-Tree bindings for tilcdc DRM generic panel output driver
4 - compatible: value should be "ti,tilcdc,panel".
5 - panel-info: configuration info to configure LCDC correctly for the panel
6 - ac-bias: AC Bias Pin Frequency
7 - ac-bias-intrpt: AC Bias Pin Transitions per Interrupt
8 - dma-burst-sz: DMA burst size
9 - bpp: Bits per pixel
10 - fdd: FIFO DMA Request Delay
11 - sync-edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling
12 - sync-ctrl: Horizontal and Vertical Sync: Control: 0=ignore
[all …]
/openbmc/linux/drivers/platform/x86/x86-android-tablets/
H A Dshared-psy-info.c1 // SPDX-License-Identifier: GPL-2.0-or-later
8 * Copyright (C) 2021-2023 Hans de Goede <hdegoede@redhat.com>
17 #include "shared-psy-info.h"
19 /* Generic / shared charger / battery settings */
20 const char * const tusb1211_chg_det_psy[] = { "tusb1211-charger-detect" };
21 const char * const bq24190_psy[] = { "bq24190-charger" };
22 const char * const bq25890_psy[] = { "bq25890-charger-0" };
25 PROPERTY_ENTRY_STRING_ARRAY("supplied-from", bq24190_psy),
34 PROPERTY_ENTRY_STRING_ARRAY("supplied-from", bq25890_psy),
42 /* LiPo HighVoltage (max 4.35V) settings used by most devs with a HV bat. */
[all …]

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