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/openbmc/u-boot/board/sbc8548/
H A Dtlb.c1 // SPDX-License-Identifier: GPL-2.0+
13 /* TLB 0 - for temp stack in cache */
31 * TLB 0: 64M Non-cacheable, guarded
44 * TLB 1: 1G Non-cacheable, guarded
53 * TLB 2: 64M Non-cacheable, guarded
64 * TLB 3: 64M Cacheable, non-guarded
72 * TLB 4: 64M Cacheable, non-guarded
82 * TLB 5: 16M Cacheable, non-guarded
83 * 0xf8000000 1M 7-segment LED display
94 * TLB 6: 64M Non-cacheable, guarded
[all …]
/openbmc/u-boot/board/freescale/mpc8541cds/
H A Dtlb.c1 // SPDX-License-Identifier: GPL-2.0+
13 /* TLB 0 - for temp stack in cache */
28 * TLB 0: 16M Non-cacheable, guarded
37 * TLB 1: 256M Non-cacheable, guarded
45 * TLB 2: 256M Non-cacheable, guarded
53 * TLB 3: 256M Non-cacheable, guarded
61 * TLB 4: 256M Non-cacheable, guarded
69 * TLB 5: 64M Non-cacheable, guarded
79 * TLB 6: 64M Cacheable, non-guarded
87 * TLB 7: 1M Non-cacheable, guarded
/openbmc/u-boot/board/freescale/mpc8555cds/
H A Dtlb.c1 // SPDX-License-Identifier: GPL-2.0+
13 /* TLB 0 - for temp stack in cache */
28 * TLB 0: 16M Non-cacheable, guarded
37 * TLB 1: 256M Non-cacheable, guarded
45 * TLB 2: 256M Non-cacheable, guarded
53 * TLB 3: 256M Non-cacheable, guarded
61 * TLB 4: 256M Non-cacheable, guarded
69 * TLB 5: 64M Non-cacheable, guarded
79 * TLB 6: 64M Cacheable, non-guarded
87 * TLB 7: 1M Non-cacheable, guarded
/openbmc/u-boot/board/freescale/mpc8548cds/
H A Dtlb.c1 // SPDX-License-Identifier: GPL-2.0+
13 /* TLB 0 - for temp stack in cache */
30 * FLASH(cover boot page) 16M Non-cacheable, guarded
38 * CCSRBAR 1M Non-cacheable, guarded
46 * LBC SDRAM 64M Cacheable, non-guarded
55 * CADMUS registers 1M Non-cacheable, guarded
63 * PCI and PCIe MEM 1G Non-cacheable, guarded
71 * PCI1 IO 1M Non-cacheable, guarded
79 * PCIe IO 1M Non-cacheable, guarded
/openbmc/u-boot/include/configs/
H A DMPC8548CDS.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor.
24 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
85 * 0x0000_0000 0x7fff_ffff DDR 2G cacheable
86 * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M cacheable
87 * 0xa000_0000 0xbfff_ffff PCIe MEM 512M cacheable
88 * 0xc000_0000 0xdfff_ffff RapidIO 512M cacheable
89 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
90 * 0xe200_0000 0xe20f_ffff PCI1 IO 1M non-cacheable
91 * 0xe300_0000 0xe30f_ffff PCIe IO 1M non-cacheable
[all …]
H A DP1023RDB.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Authors: Roy Zang <tie-fei.zang@freescale.com>
28 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
70 * 0x0000_0000 0x1fff_ffff DDR 512M cacheable
71 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
72 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
73 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
74 * 0xff00_0000 0xff3f_ffff DPAA_QBMAN 4M cacheable
75 * 0xff60_0000 0xff7f_ffff CCSR 2M non-cacheable
76 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable TLB0
[all …]
H A DMPC8544DS.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2007, 2010-2011 Freescale Semiconductor, Inc.
20 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
74 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
76 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
78 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
80 * 0xe000_0000 0xe00f_ffff CCSR 1M non-cacheable
81 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
83 * Localbus cacheable
85 * 0xf000_0000 0xf3ff_ffff SDRAM 64M Cacheable
[all …]
H A Dxpedite537x.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright 2007-2008 Freescale Semiconductor, Inc.
24 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
80 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
81 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
82 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
83 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
84 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
85 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
86 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
[all …]
H A DP1022DS.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2010-2012 Freescale Semiconductor, Inc.
15 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
24 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
34 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
43 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
79 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
80 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
94 #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
170 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
[all …]
H A Dcontrolcenterd.h23 * MA 02111-1307 USA
85 * 0x0000_0000 0x3fff_ffff DDR 1G Cacheable
86 * 0xc000_0000 0xdfff_ffff PCI Express Mem 512M non-cacheable
87 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
89 * Localbus non-cacheable
90 * 0xe000_0000 0xe00f_ffff eLBC 1M non-cacheable
91 * 0xf8fc0000 0xf8ff_ffff L2 SRAM 256k Cacheable
92 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
93 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
100 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
[all …]
H A Dxpedite517x.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright 2007-2008 Freescale Semiconductor, Inc.
28 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
68 * Base addresses -- Note these are effective addresses where the
89 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
90 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
91 * 0xc000_0000 0xcfff_ffff PCIe2 Mem 256M non-cacheable
92 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
93 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
94 * 0xe880_0000 0xe8ff_ffff PCIe2 IO 8M non-cacheable
[all …]
H A DMPC8572DS.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc.
31 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
128 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
129 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
130 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
131 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
133 * Localbus cacheable (TBD)
134 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
136 * Localbus non-cacheable
[all …]
H A DMPC8536DS.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright 2007-2009,2010-2012 Freescale Semiconductor, Inc.
40 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
63 #define CONFIG_SYS_MEMTEST_END 0x1f000000 /* skip u-boot at top of RAM */
132 * Memory map -- xxx -this is wrong, needs updating
134 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
135 * 0x8000_0000 0xbfff_ffff PCI Express Mem 1G non-cacheable
136 * 0xc000_0000 0xdfff_ffff PCI 512M non-cacheable
137 * 0xe100_0000 0xe3ff_ffff PCI IO range 4M non-cacheable
139 * Localbus cacheable (TBD)
[all …]
H A Dxpedite550x.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright 2007-2008 Freescale Semiconductor, Inc.
24 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
84 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
85 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
86 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
87 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
88 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
89 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
90 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
[all …]
H A Dxpedite520x.h1 /* SPDX-License-Identifier: GPL-2.0+ */
4 * Copyright 2004-2008 Freescale Semiconductor, Inc.
23 #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
67 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
68 * 0x8000_0000 0xbfff_ffff PCI1 Mem 1G non-cacheable
69 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
70 * 0xe800_0000 0xe87f_ffff PCI1 IO 8M non-cacheable
71 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
72 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
73 * 0xf800_0000 0xfbff_ffff NOR Flash 2 64M non-cacheable
[all …]
/openbmc/u-boot/board/freescale/mpc8544ds/
H A Dtlb.c1 // SPDX-License-Identifier: GPL-2.0+
13 /* TLB 0 - for temp stack in cache */
27 * TLB 0: 64M Non-cacheable, guarded
35 * TLB 1: 1G Non-cacheable, guarded
43 * TLB 2: 256M Non-cacheable, guarded
50 * TLB 3: 256M Non-cacheable, guarded
57 * TLB 4: 64M Non-cacheable, guarded
66 * TLB 5: 64M Non-cacheable, guarded
67 * 0xf8000000 64M PIXIS 0xF8000000 - 0xFBFFFFFF
/openbmc/u-boot/board/freescale/mpc8568mds/
H A Dtlb.c1 // SPDX-License-Identifier: GPL-2.0+
13 /* TLB 0 - for temp stack in cache */
29 * TLBe 0: 16M Non-cacheable, guarded
38 * TLBe 1: 16M Non-cacheable, guarded
46 * TLBe 2: 1G Non-cacheable, guarded
55 * TLBe 3: 64M Non-cacheable, guarded
65 * TLBe 4: 64M Cacheable, non-guarded
73 * TLBe 5: 256K Non-cacheable, guarded
/openbmc/u-boot/board/socrates/
H A Dtlb.c1 // SPDX-License-Identifier: GPL-2.0+
16 /* TLB 0 - for temp stack in cache */
32 * TLB 1: 64M Non-cacheable, guarded
41 * TLB 2: 256M Non-cacheable, guarded
49 * TLB 3: 256M Non-cacheable, guarded
58 * TLB 4: 1M Non-cacheable, guarded
67 * TLB 5: 64M Non-cacheable, guarded
78 * TLB 6: 64M Non-cacheable, guarded
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen1/
H A Dcache.json5 …s transferred from IC pipe to DE instruction decoder (includes non-cacheable and cacheable fill re…
35 … instruction stream was being modified by another processor in an MP system - typically a highly u…
52 …l. IC pipe was stalled during this clock cycle (including IC to OC fetches) due to back-pressure.",
58 …be (external or LS). The number of instruction cache lines invalidated. A non-SMC event is CMC (cr…
64 …iting fill response. The number of instruction cache lines invalidated. A non-SMC event is CMC (cr…
75 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
81 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
87 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
93 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
99 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request…
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen3/
H A Dcache.json5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …riefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
/openbmc/linux/tools/perf/pmu-events/arch/x86/amdzen2/
H A Dcache.json5 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache reads (including har…
11 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache stores.",
17 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache shared reads.",
23 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Instruction cache reads.",
29 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). Data cache state change request…
35 "BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). PrefetchL2Cmd.",
41 …"BriefDescription": "All L2 Cache Requests (Breakdown 1 - Common). L2 Prefetcher. All prefetches a…
64 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized.",
70 …riefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Data cache read sized non-cacheable…
76 "BriefDescription": "All L2 Cache Requests (Breakdown 2 - Rare). Instruction cache read sized.",
[all …]
/openbmc/u-boot/board/freescale/mpc8569mds/
H A Dtlb.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2010 Freescale Semiconductor, Inc.
13 /* TLB 0 - for temp stack in cache */
32 * TLBe 0: 64M write-through, guarded
47 * TLBe 1: 256KB Non-cacheable, guarded
57 * TLBe 2: 256M Non-cacheable, guarded
65 * TLBe 3: 256M Non-cacheable, guarded
74 * TLBe 4: 64M Non-cacheable, guarded
83 /* *I*G - L2SRAM */
/openbmc/linux/tools/perf/pmu-events/arch/x86/icelakex/
H A Dcache.json6 …opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
14 …ted due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable dema…
24 …ted due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable dema…
32 … waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable dema…
40 …non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined u…
70 …"BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered…
73 …y an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
89 …from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are …
145 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
153 "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
[all …]
/openbmc/u-boot/board/freescale/p1010rdb/
H A DREADME.P1010RDB-PA5 The P1010 is a cost-effective, low-power, highly integrated host processor
14 - 1Gbyte unbuffered DDR3 SDRAM discrete devices (32-bit bus)
15 - 32 Mbyte NOR flash single-chip memory
16 - 32 Mbyte NAND flash memory
17 - 256 Kbit M24256 I2C EEPROM
18 - 16 Mbyte SPI memory
19 - I2C Board EEPROM 128x8 bit memory
20 - SD/MMC connector to interface with the SD memory card
22 - PCIe:
23 - Lane0: x1 mini-PCIe slot
[all …]
H A DREADME.P1010RDB-PB3 The P1010RDB-PB is a Freescale Reference Design Board that hosts the P1010 SoC.
4 P1010RDB-PB is a variation of previous P1010RDB-PA board.
6 The P1010 is a cost-effective, low-power, highly integrated host processor
13 The P1010RDB-PB board features are as following:
15 - 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus)
16 - 32M bytes NOR flash single-chip memory
17 - 2G bytes NAND flash memory
18 - 16M bytes SPI memory
19 - 256K bit M24256 I2C EEPROM
20 - I2C Board EEPROM 128x8 bit memory
[all …]

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