xref: /openbmc/linux/tools/perf/pmu-events/arch/x86/icelakex/cache.json (revision 1ac731c529cd4d6adbce134754b51ff7d822b145)
1cdb29a8fSJin Yao[
2cdb29a8fSJin Yao    {
309625cffSIan Rogers        "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
409625cffSIan Rogers        "EventCode": "0x51",
509625cffSIan Rogers        "EventName": "L1D.REPLACEMENT",
609625cffSIan Rogers        "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
7cdb29a8fSJin Yao        "SampleAfterValue": "100003",
8cdb29a8fSJin Yao        "UMask": "0x1"
9cdb29a8fSJin Yao    },
10cdb29a8fSJin Yao    {
11cdb29a8fSJin Yao        "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
12cdb29a8fSJin Yao        "EventCode": "0x48",
13cdb29a8fSJin Yao        "EventName": "L1D_PEND_MISS.FB_FULL",
14bd035250SIan Rogers        "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
15cdb29a8fSJin Yao        "SampleAfterValue": "1000003",
16cdb29a8fSJin Yao        "UMask": "0x2"
17cdb29a8fSJin Yao    },
18cdb29a8fSJin Yao    {
19bd035250SIan Rogers        "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
20cdb29a8fSJin Yao        "CounterMask": "1",
21cdb29a8fSJin Yao        "EdgeDetect": "1",
22cdb29a8fSJin Yao        "EventCode": "0x48",
23cdb29a8fSJin Yao        "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS",
24bd035250SIan Rogers        "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
25cdb29a8fSJin Yao        "SampleAfterValue": "1000003",
26cdb29a8fSJin Yao        "UMask": "0x2"
27cdb29a8fSJin Yao    },
28cdb29a8fSJin Yao    {
29cdb29a8fSJin Yao        "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
30cdb29a8fSJin Yao        "EventCode": "0x48",
31cdb29a8fSJin Yao        "EventName": "L1D_PEND_MISS.L2_STALL",
32cdb29a8fSJin Yao        "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
33cdb29a8fSJin Yao        "SampleAfterValue": "1000003",
34cdb29a8fSJin Yao        "UMask": "0x4"
35cdb29a8fSJin Yao    },
36cdb29a8fSJin Yao    {
3709625cffSIan Rogers        "BriefDescription": "Number of L1D misses that are outstanding",
3809625cffSIan Rogers        "EventCode": "0x48",
3909625cffSIan Rogers        "EventName": "L1D_PEND_MISS.PENDING",
4009625cffSIan Rogers        "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
4109625cffSIan Rogers        "SampleAfterValue": "1000003",
42cdb29a8fSJin Yao        "UMask": "0x1"
43cdb29a8fSJin Yao    },
44cdb29a8fSJin Yao    {
4509625cffSIan Rogers        "BriefDescription": "Cycles with L1D load Misses outstanding.",
46cdb29a8fSJin Yao        "CounterMask": "1",
4709625cffSIan Rogers        "EventCode": "0x48",
4809625cffSIan Rogers        "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
4909625cffSIan Rogers        "PublicDescription": "Counts duration of L1D miss outstanding in cycles.",
50cdb29a8fSJin Yao        "SampleAfterValue": "1000003",
51cdb29a8fSJin Yao        "UMask": "0x1"
52cdb29a8fSJin Yao    },
53cdb29a8fSJin Yao    {
5409625cffSIan Rogers        "BriefDescription": "L2 cache lines filling L2",
5509625cffSIan Rogers        "EventCode": "0xF1",
5609625cffSIan Rogers        "EventName": "L2_LINES_IN.ALL",
5709625cffSIan Rogers        "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
58cdb29a8fSJin Yao        "SampleAfterValue": "100003",
5909625cffSIan Rogers        "UMask": "0x1f"
60cdb29a8fSJin Yao    },
61cdb29a8fSJin Yao    {
6209625cffSIan Rogers        "BriefDescription": "Cache lines that are evicted by L2 cache when triggered by an L2 cache fill.",
6309625cffSIan Rogers        "EventCode": "0xF2",
6409625cffSIan Rogers        "EventName": "L2_LINES_OUT.NON_SILENT",
6509625cffSIan Rogers        "PublicDescription": "Counts the number of lines that are evicted by the L2 cache due to L2 cache fills.  Evicted lines are delivered to the L3, which may or may not cache them, according to system load and priorities.",
6609625cffSIan Rogers        "SampleAfterValue": "200003",
6709625cffSIan Rogers        "UMask": "0x2"
68cdb29a8fSJin Yao    },
69cdb29a8fSJin Yao    {
7009625cffSIan Rogers        "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache when triggered by an L2 cache fill.",
7109625cffSIan Rogers        "EventCode": "0xF2",
7209625cffSIan Rogers        "EventName": "L2_LINES_OUT.SILENT",
7309625cffSIan Rogers        "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache when triggered by an L2 cache fill. These lines are typically in Shared or Exclusive state. A non-threaded event.",
7409625cffSIan Rogers        "SampleAfterValue": "200003",
7509625cffSIan Rogers        "UMask": "0x1"
7609625cffSIan Rogers    },
7709625cffSIan Rogers    {
7809625cffSIan Rogers        "BriefDescription": "L2 code requests",
7909625cffSIan Rogers        "EventCode": "0x24",
8009625cffSIan Rogers        "EventName": "L2_RQSTS.ALL_CODE_RD",
8109625cffSIan Rogers        "PublicDescription": "Counts the total number of L2 code requests.",
8209625cffSIan Rogers        "SampleAfterValue": "200003",
8309625cffSIan Rogers        "UMask": "0xe4"
8409625cffSIan Rogers    },
8509625cffSIan Rogers    {
8609625cffSIan Rogers        "BriefDescription": "Demand Data Read requests",
8709625cffSIan Rogers        "EventCode": "0x24",
8809625cffSIan Rogers        "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
8909625cffSIan Rogers        "PublicDescription": "Counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
9009625cffSIan Rogers        "SampleAfterValue": "200003",
9109625cffSIan Rogers        "UMask": "0xe1"
9209625cffSIan Rogers    },
9309625cffSIan Rogers    {
9409625cffSIan Rogers        "BriefDescription": "Demand requests that miss L2 cache",
9509625cffSIan Rogers        "EventCode": "0x24",
9609625cffSIan Rogers        "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
9709625cffSIan Rogers        "PublicDescription": "Counts demand requests that miss L2 cache.",
9809625cffSIan Rogers        "SampleAfterValue": "200003",
9909625cffSIan Rogers        "UMask": "0x27"
10009625cffSIan Rogers    },
10109625cffSIan Rogers    {
10209625cffSIan Rogers        "BriefDescription": "RFO requests to L2 cache",
10309625cffSIan Rogers        "EventCode": "0x24",
10409625cffSIan Rogers        "EventName": "L2_RQSTS.ALL_RFO",
10509625cffSIan Rogers        "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
10609625cffSIan Rogers        "SampleAfterValue": "200003",
10709625cffSIan Rogers        "UMask": "0xe2"
10809625cffSIan Rogers    },
10909625cffSIan Rogers    {
11009625cffSIan Rogers        "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
11109625cffSIan Rogers        "EventCode": "0x24",
11209625cffSIan Rogers        "EventName": "L2_RQSTS.CODE_RD_HIT",
11309625cffSIan Rogers        "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
11409625cffSIan Rogers        "SampleAfterValue": "200003",
11509625cffSIan Rogers        "UMask": "0xc4"
11609625cffSIan Rogers    },
11709625cffSIan Rogers    {
11809625cffSIan Rogers        "BriefDescription": "L2 cache misses when fetching instructions",
11909625cffSIan Rogers        "EventCode": "0x24",
12009625cffSIan Rogers        "EventName": "L2_RQSTS.CODE_RD_MISS",
12109625cffSIan Rogers        "PublicDescription": "Counts L2 cache misses when fetching instructions.",
12209625cffSIan Rogers        "SampleAfterValue": "200003",
12309625cffSIan Rogers        "UMask": "0x24"
12409625cffSIan Rogers    },
12509625cffSIan Rogers    {
12609625cffSIan Rogers        "BriefDescription": "Demand Data Read requests that hit L2 cache",
12709625cffSIan Rogers        "EventCode": "0x24",
12809625cffSIan Rogers        "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
12909625cffSIan Rogers        "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.",
13009625cffSIan Rogers        "SampleAfterValue": "200003",
13109625cffSIan Rogers        "UMask": "0xc1"
13209625cffSIan Rogers    },
13309625cffSIan Rogers    {
13409625cffSIan Rogers        "BriefDescription": "Demand Data Read miss L2, no rejects",
13509625cffSIan Rogers        "EventCode": "0x24",
13609625cffSIan Rogers        "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
13709625cffSIan Rogers        "PublicDescription": "Counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
13809625cffSIan Rogers        "SampleAfterValue": "200003",
13909625cffSIan Rogers        "UMask": "0x21"
14009625cffSIan Rogers    },
14109625cffSIan Rogers    {
14209625cffSIan Rogers        "BriefDescription": "RFO requests that hit L2 cache",
14309625cffSIan Rogers        "EventCode": "0x24",
14409625cffSIan Rogers        "EventName": "L2_RQSTS.RFO_HIT",
14509625cffSIan Rogers        "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
14609625cffSIan Rogers        "SampleAfterValue": "200003",
14709625cffSIan Rogers        "UMask": "0xc2"
14809625cffSIan Rogers    },
14909625cffSIan Rogers    {
15009625cffSIan Rogers        "BriefDescription": "RFO requests that miss L2 cache",
15109625cffSIan Rogers        "EventCode": "0x24",
15209625cffSIan Rogers        "EventName": "L2_RQSTS.RFO_MISS",
15309625cffSIan Rogers        "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
15409625cffSIan Rogers        "SampleAfterValue": "200003",
15509625cffSIan Rogers        "UMask": "0x22"
15609625cffSIan Rogers    },
15709625cffSIan Rogers    {
15809625cffSIan Rogers        "BriefDescription": "SW prefetch requests that hit L2 cache.",
15909625cffSIan Rogers        "EventCode": "0x24",
16009625cffSIan Rogers        "EventName": "L2_RQSTS.SWPF_HIT",
16109625cffSIan Rogers        "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
16209625cffSIan Rogers        "SampleAfterValue": "200003",
16309625cffSIan Rogers        "UMask": "0xc8"
16409625cffSIan Rogers    },
16509625cffSIan Rogers    {
16609625cffSIan Rogers        "BriefDescription": "SW prefetch requests that miss L2 cache.",
16709625cffSIan Rogers        "EventCode": "0x24",
16809625cffSIan Rogers        "EventName": "L2_RQSTS.SWPF_MISS",
16909625cffSIan Rogers        "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
17009625cffSIan Rogers        "SampleAfterValue": "200003",
17109625cffSIan Rogers        "UMask": "0x28"
17209625cffSIan Rogers    },
17309625cffSIan Rogers    {
17409625cffSIan Rogers        "BriefDescription": "L2 writebacks that access L2 cache",
17509625cffSIan Rogers        "EventCode": "0xF0",
17609625cffSIan Rogers        "EventName": "L2_TRANS.L2_WB",
17709625cffSIan Rogers        "PublicDescription": "Counts L2 writebacks that access L2 cache.",
17809625cffSIan Rogers        "SampleAfterValue": "200003",
17909625cffSIan Rogers        "UMask": "0x40"
18009625cffSIan Rogers    },
18109625cffSIan Rogers    {
18209625cffSIan Rogers        "BriefDescription": "Core-originated cacheable requests that missed L3  (Except hardware prefetches to the L3)",
18309625cffSIan Rogers        "EventCode": "0x2e",
18409625cffSIan Rogers        "EventName": "LONGEST_LAT_CACHE.MISS",
18509625cffSIan Rogers        "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2.  It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
18609625cffSIan Rogers        "SampleAfterValue": "100003",
18709625cffSIan Rogers        "UMask": "0x41"
18809625cffSIan Rogers    },
18909625cffSIan Rogers    {
19009625cffSIan Rogers        "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
19109625cffSIan Rogers        "EventCode": "0x2e",
19209625cffSIan Rogers        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
19309625cffSIan Rogers        "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2.  It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
19409625cffSIan Rogers        "SampleAfterValue": "100003",
19509625cffSIan Rogers        "UMask": "0x4f"
19609625cffSIan Rogers    },
19709625cffSIan Rogers    {
198d214d0c2SIan Rogers        "BriefDescription": "Retired load instructions.",
199cdb29a8fSJin Yao        "Data_LA": "1",
200cdb29a8fSJin Yao        "EventCode": "0xd0",
20109625cffSIan Rogers        "EventName": "MEM_INST_RETIRED.ALL_LOADS",
202cdb29a8fSJin Yao        "PEBS": "1",
203d214d0c2SIan Rogers        "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.",
20409625cffSIan Rogers        "SampleAfterValue": "1000003",
20509625cffSIan Rogers        "UMask": "0x81"
206cdb29a8fSJin Yao    },
207cdb29a8fSJin Yao    {
208d214d0c2SIan Rogers        "BriefDescription": "Retired store instructions.",
209cdb29a8fSJin Yao        "Data_LA": "1",
210cdb29a8fSJin Yao        "EventCode": "0xd0",
21109625cffSIan Rogers        "EventName": "MEM_INST_RETIRED.ALL_STORES",
212cdb29a8fSJin Yao        "PEBS": "1",
213d214d0c2SIan Rogers        "PublicDescription": "Counts all retired store instructions.",
21409625cffSIan Rogers        "SampleAfterValue": "1000003",
21509625cffSIan Rogers        "UMask": "0x82"
21609625cffSIan Rogers    },
21709625cffSIan Rogers    {
21809625cffSIan Rogers        "BriefDescription": "All retired memory instructions.",
21909625cffSIan Rogers        "Data_LA": "1",
22009625cffSIan Rogers        "EventCode": "0xd0",
22109625cffSIan Rogers        "EventName": "MEM_INST_RETIRED.ANY",
22209625cffSIan Rogers        "PEBS": "1",
22309625cffSIan Rogers        "PublicDescription": "Counts all retired memory instructions - loads and stores.",
22409625cffSIan Rogers        "SampleAfterValue": "1000003",
22509625cffSIan Rogers        "UMask": "0x83"
226cdb29a8fSJin Yao    },
227cdb29a8fSJin Yao    {
228cdb29a8fSJin Yao        "BriefDescription": "Retired load instructions with locked access.",
229cdb29a8fSJin Yao        "Data_LA": "1",
230cdb29a8fSJin Yao        "EventCode": "0xd0",
231cdb29a8fSJin Yao        "EventName": "MEM_INST_RETIRED.LOCK_LOADS",
232cdb29a8fSJin Yao        "PEBS": "1",
233cdb29a8fSJin Yao        "PublicDescription": "Counts retired load instructions with locked access.",
234cdb29a8fSJin Yao        "SampleAfterValue": "100007",
235cdb29a8fSJin Yao        "UMask": "0x21"
236cdb29a8fSJin Yao    },
237cdb29a8fSJin Yao    {
238cdb29a8fSJin Yao        "BriefDescription": "Retired load instructions that split across a cacheline boundary.",
239cdb29a8fSJin Yao        "Data_LA": "1",
240cdb29a8fSJin Yao        "EventCode": "0xd0",
241cdb29a8fSJin Yao        "EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
242cdb29a8fSJin Yao        "PEBS": "1",
243cdb29a8fSJin Yao        "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.",
244cdb29a8fSJin Yao        "SampleAfterValue": "100003",
245cdb29a8fSJin Yao        "UMask": "0x41"
246cdb29a8fSJin Yao    },
247cdb29a8fSJin Yao    {
248cdb29a8fSJin Yao        "BriefDescription": "Retired store instructions that split across a cacheline boundary.",
249cdb29a8fSJin Yao        "Data_LA": "1",
250cdb29a8fSJin Yao        "EventCode": "0xd0",
251cdb29a8fSJin Yao        "EventName": "MEM_INST_RETIRED.SPLIT_STORES",
252cdb29a8fSJin Yao        "PEBS": "1",
253cdb29a8fSJin Yao        "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
254cdb29a8fSJin Yao        "SampleAfterValue": "100003",
255cdb29a8fSJin Yao        "UMask": "0x42"
256cdb29a8fSJin Yao    },
257cdb29a8fSJin Yao    {
25809625cffSIan Rogers        "BriefDescription": "Retired load instructions that miss the STLB.",
259cdb29a8fSJin Yao        "Data_LA": "1",
260cdb29a8fSJin Yao        "EventCode": "0xd0",
26109625cffSIan Rogers        "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
262cdb29a8fSJin Yao        "PEBS": "1",
26309625cffSIan Rogers        "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).",
26409625cffSIan Rogers        "SampleAfterValue": "100003",
26509625cffSIan Rogers        "UMask": "0x11"
266cdb29a8fSJin Yao    },
267cdb29a8fSJin Yao    {
26809625cffSIan Rogers        "BriefDescription": "Retired store instructions that miss the STLB.",
269cdb29a8fSJin Yao        "Data_LA": "1",
270cdb29a8fSJin Yao        "EventCode": "0xd0",
27109625cffSIan Rogers        "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
272cdb29a8fSJin Yao        "PEBS": "1",
27309625cffSIan Rogers        "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).",
274cdb29a8fSJin Yao        "SampleAfterValue": "100003",
27509625cffSIan Rogers        "UMask": "0x12"
276cdb29a8fSJin Yao    },
277cdb29a8fSJin Yao    {
278cdb29a8fSJin Yao        "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
279cdb29a8fSJin Yao        "Data_LA": "1",
280cdb29a8fSJin Yao        "EventCode": "0xd2",
281cdb29a8fSJin Yao        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",
282cdb29a8fSJin Yao        "PEBS": "1",
283cdb29a8fSJin Yao        "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3.",
284cdb29a8fSJin Yao        "SampleAfterValue": "20011",
285cdb29a8fSJin Yao        "UMask": "0x4"
286cdb29a8fSJin Yao    },
287cdb29a8fSJin Yao    {
28809625cffSIan Rogers        "BriefDescription": "This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
28909625cffSIan Rogers        "Data_LA": "1",
290f8e23ad1SIan Rogers        "Deprecated": "1",
29109625cffSIan Rogers        "EventCode": "0xd2",
29209625cffSIan Rogers        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
29309625cffSIan Rogers        "PEBS": "1",
29409625cffSIan Rogers        "SampleAfterValue": "20011",
29509625cffSIan Rogers        "UMask": "0x2"
29609625cffSIan Rogers    },
29709625cffSIan Rogers    {
29809625cffSIan Rogers        "BriefDescription": "This event is deprecated. Refer to new event MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",
29909625cffSIan Rogers        "Data_LA": "1",
300f8e23ad1SIan Rogers        "Deprecated": "1",
30109625cffSIan Rogers        "EventCode": "0xd2",
30209625cffSIan Rogers        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
30309625cffSIan Rogers        "PEBS": "1",
30409625cffSIan Rogers        "SampleAfterValue": "20011",
30509625cffSIan Rogers        "UMask": "0x4"
30609625cffSIan Rogers    },
30709625cffSIan Rogers    {
30809625cffSIan Rogers        "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
30909625cffSIan Rogers        "Data_LA": "1",
31009625cffSIan Rogers        "EventCode": "0xd2",
31109625cffSIan Rogers        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
31209625cffSIan Rogers        "PEBS": "1",
31309625cffSIan Rogers        "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
31409625cffSIan Rogers        "SampleAfterValue": "20011",
31509625cffSIan Rogers        "UMask": "0x1"
31609625cffSIan Rogers    },
31709625cffSIan Rogers    {
318cdb29a8fSJin Yao        "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required",
319cdb29a8fSJin Yao        "Data_LA": "1",
320cdb29a8fSJin Yao        "EventCode": "0xd2",
321cdb29a8fSJin Yao        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
322cdb29a8fSJin Yao        "PEBS": "1",
323cdb29a8fSJin Yao        "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.",
324cdb29a8fSJin Yao        "SampleAfterValue": "100003",
325cdb29a8fSJin Yao        "UMask": "0x8"
326cdb29a8fSJin Yao    },
327cdb29a8fSJin Yao    {
32809625cffSIan Rogers        "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
32909625cffSIan Rogers        "Data_LA": "1",
33009625cffSIan Rogers        "EventCode": "0xd2",
33109625cffSIan Rogers        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
33209625cffSIan Rogers        "PEBS": "1",
33309625cffSIan Rogers        "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache.",
33409625cffSIan Rogers        "SampleAfterValue": "20011",
33509625cffSIan Rogers        "UMask": "0x2"
33609625cffSIan Rogers    },
33709625cffSIan Rogers    {
338cdb29a8fSJin Yao        "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram",
339cdb29a8fSJin Yao        "Data_LA": "1",
340cdb29a8fSJin Yao        "EventCode": "0xd3",
341cdb29a8fSJin Yao        "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM",
342cdb29a8fSJin Yao        "PEBS": "1",
343cdb29a8fSJin Yao        "PublicDescription": "Retired load instructions which data sources missed L3 but serviced from local DRAM.",
344cdb29a8fSJin Yao        "SampleAfterValue": "100007",
345cdb29a8fSJin Yao        "UMask": "0x1"
346cdb29a8fSJin Yao    },
347cdb29a8fSJin Yao    {
348cdb29a8fSJin Yao        "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from remote dram",
349cdb29a8fSJin Yao        "Data_LA": "1",
350cdb29a8fSJin Yao        "EventCode": "0xd3",
351cdb29a8fSJin Yao        "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_DRAM",
352cdb29a8fSJin Yao        "PEBS": "1",
353cdb29a8fSJin Yao        "SampleAfterValue": "100007",
354cdb29a8fSJin Yao        "UMask": "0x2"
355cdb29a8fSJin Yao    },
356cdb29a8fSJin Yao    {
357cdb29a8fSJin Yao        "BriefDescription": "Retired load instructions whose data sources was forwarded from a remote cache",
358cdb29a8fSJin Yao        "Data_LA": "1",
359cdb29a8fSJin Yao        "EventCode": "0xd3",
360cdb29a8fSJin Yao        "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_FWD",
361cdb29a8fSJin Yao        "PEBS": "1",
362cdb29a8fSJin Yao        "PublicDescription": "Retired load instructions whose data sources was forwarded from a remote cache.",
363cdb29a8fSJin Yao        "SampleAfterValue": "100007",
364cdb29a8fSJin Yao        "UMask": "0x8"
365cdb29a8fSJin Yao    },
366cdb29a8fSJin Yao    {
36709625cffSIan Rogers        "BriefDescription": "Retired load instructions whose data sources was remote HITM",
36809625cffSIan Rogers        "Data_LA": "1",
36909625cffSIan Rogers        "EventCode": "0xd3",
37009625cffSIan Rogers        "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_HITM",
37109625cffSIan Rogers        "PEBS": "1",
37209625cffSIan Rogers        "PublicDescription": "Retired load instructions whose data sources was remote HITM.",
37309625cffSIan Rogers        "SampleAfterValue": "100007",
37409625cffSIan Rogers        "UMask": "0x4"
37509625cffSIan Rogers    },
37609625cffSIan Rogers    {
377f8e23ad1SIan Rogers        "BriefDescription": "Retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.",
378cdb29a8fSJin Yao        "Data_LA": "1",
379cdb29a8fSJin Yao        "EventCode": "0xd3",
380cdb29a8fSJin Yao        "EventName": "MEM_LOAD_L3_MISS_RETIRED.REMOTE_PMM",
381cdb29a8fSJin Yao        "PEBS": "1",
382f8e23ad1SIan Rogers        "PublicDescription": "Counts retired load instructions with remote Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode).",
383cdb29a8fSJin Yao        "SampleAfterValue": "100007",
384cdb29a8fSJin Yao        "UMask": "0x10"
385cdb29a8fSJin Yao    },
386cdb29a8fSJin Yao    {
38709625cffSIan Rogers        "BriefDescription": "Retired instructions with at least 1 uncacheable load or Bus Lock.",
38809625cffSIan Rogers        "Data_LA": "1",
38909625cffSIan Rogers        "EventCode": "0xd4",
39009625cffSIan Rogers        "EventName": "MEM_LOAD_MISC_RETIRED.UC",
39109625cffSIan Rogers        "PEBS": "1",
39209625cffSIan Rogers        "PublicDescription": "Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock).",
39309625cffSIan Rogers        "SampleAfterValue": "100007",
39409625cffSIan Rogers        "UMask": "0x4"
39509625cffSIan Rogers    },
39609625cffSIan Rogers    {
39709625cffSIan Rogers        "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.",
39809625cffSIan Rogers        "Data_LA": "1",
39909625cffSIan Rogers        "EventCode": "0xd1",
40009625cffSIan Rogers        "EventName": "MEM_LOAD_RETIRED.FB_HIT",
40109625cffSIan Rogers        "PEBS": "1",
40209625cffSIan Rogers        "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.",
40309625cffSIan Rogers        "SampleAfterValue": "100007",
404cdb29a8fSJin Yao        "UMask": "0x40"
405cdb29a8fSJin Yao    },
406cdb29a8fSJin Yao    {
40709625cffSIan Rogers        "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
40809625cffSIan Rogers        "Data_LA": "1",
40909625cffSIan Rogers        "EventCode": "0xd1",
41009625cffSIan Rogers        "EventName": "MEM_LOAD_RETIRED.L1_HIT",
41109625cffSIan Rogers        "PEBS": "1",
41209625cffSIan Rogers        "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.",
41309625cffSIan Rogers        "SampleAfterValue": "1000003",
41409625cffSIan Rogers        "UMask": "0x1"
415cdb29a8fSJin Yao    },
416cdb29a8fSJin Yao    {
41709625cffSIan Rogers        "BriefDescription": "Retired load instructions missed L1 cache as data sources",
41809625cffSIan Rogers        "Data_LA": "1",
41909625cffSIan Rogers        "EventCode": "0xd1",
42009625cffSIan Rogers        "EventName": "MEM_LOAD_RETIRED.L1_MISS",
42109625cffSIan Rogers        "PEBS": "1",
42209625cffSIan Rogers        "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.",
423cdb29a8fSJin Yao        "SampleAfterValue": "200003",
42409625cffSIan Rogers        "UMask": "0x8"
42509625cffSIan Rogers    },
42609625cffSIan Rogers    {
42709625cffSIan Rogers        "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
42809625cffSIan Rogers        "Data_LA": "1",
42909625cffSIan Rogers        "EventCode": "0xd1",
43009625cffSIan Rogers        "EventName": "MEM_LOAD_RETIRED.L2_HIT",
43109625cffSIan Rogers        "PEBS": "1",
43209625cffSIan Rogers        "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.",
43309625cffSIan Rogers        "SampleAfterValue": "200003",
43409625cffSIan Rogers        "UMask": "0x2"
43509625cffSIan Rogers    },
43609625cffSIan Rogers    {
43709625cffSIan Rogers        "BriefDescription": "Retired load instructions missed L2 cache as data sources",
43809625cffSIan Rogers        "Data_LA": "1",
43909625cffSIan Rogers        "EventCode": "0xd1",
44009625cffSIan Rogers        "EventName": "MEM_LOAD_RETIRED.L2_MISS",
44109625cffSIan Rogers        "PEBS": "1",
44209625cffSIan Rogers        "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.",
44309625cffSIan Rogers        "SampleAfterValue": "100021",
44409625cffSIan Rogers        "UMask": "0x10"
44509625cffSIan Rogers    },
44609625cffSIan Rogers    {
44709625cffSIan Rogers        "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
44809625cffSIan Rogers        "Data_LA": "1",
44909625cffSIan Rogers        "EventCode": "0xd1",
45009625cffSIan Rogers        "EventName": "MEM_LOAD_RETIRED.L3_HIT",
45109625cffSIan Rogers        "PEBS": "1",
45209625cffSIan Rogers        "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.",
45309625cffSIan Rogers        "SampleAfterValue": "100021",
45409625cffSIan Rogers        "UMask": "0x4"
45509625cffSIan Rogers    },
45609625cffSIan Rogers    {
45709625cffSIan Rogers        "BriefDescription": "Retired load instructions missed L3 cache as data sources",
45809625cffSIan Rogers        "Data_LA": "1",
45909625cffSIan Rogers        "EventCode": "0xd1",
46009625cffSIan Rogers        "EventName": "MEM_LOAD_RETIRED.L3_MISS",
46109625cffSIan Rogers        "PEBS": "1",
46209625cffSIan Rogers        "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.",
46309625cffSIan Rogers        "SampleAfterValue": "50021",
46409625cffSIan Rogers        "UMask": "0x20"
46509625cffSIan Rogers    },
46609625cffSIan Rogers    {
467f8e23ad1SIan Rogers        "BriefDescription": "Retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source where the data request missed all caches.",
46809625cffSIan Rogers        "Data_LA": "1",
46909625cffSIan Rogers        "EventCode": "0xd1",
47009625cffSIan Rogers        "EventName": "MEM_LOAD_RETIRED.LOCAL_PMM",
47109625cffSIan Rogers        "PEBS": "1",
472f8e23ad1SIan Rogers        "PublicDescription": "Counts retired load instructions with local Intel(R) Optane(TM) DC persistent memory as the data source and the data request missed L3 (AppDirect or Memory Mode) and DRAM cache(Memory Mode).",
47309625cffSIan Rogers        "SampleAfterValue": "100003",
47409625cffSIan Rogers        "UMask": "0x80"
47509625cffSIan Rogers    },
47609625cffSIan Rogers    {
477f25db21bSIan Rogers        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit in the L3 or were snooped from another core's caches on the same socket.",
478f25db21bSIan Rogers        "EventCode": "0xB7, 0xBB",
479f25db21bSIan Rogers        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT",
480f25db21bSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
481f25db21bSIan Rogers        "MSRValue": "0x3F803C0004",
482f25db21bSIan Rogers        "SampleAfterValue": "100003",
483f25db21bSIan Rogers        "UMask": "0x1"
484f25db21bSIan Rogers    },
485f25db21bSIan Rogers    {
486f25db21bSIan Rogers        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
487f25db21bSIan Rogers        "EventCode": "0xB7, 0xBB",
488f25db21bSIan Rogers        "EventName": "OCR.DEMAND_CODE_RD.L3_HIT.SNOOP_HITM",
489f25db21bSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
490f25db21bSIan Rogers        "MSRValue": "0x10003C0004",
491f25db21bSIan Rogers        "SampleAfterValue": "100003",
492f25db21bSIan Rogers        "UMask": "0x1"
493f25db21bSIan Rogers    },
494f25db21bSIan Rogers    {
49509625cffSIan Rogers        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
49609625cffSIan Rogers        "EventCode": "0xB7, 0xBB",
49709625cffSIan Rogers        "EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HITM",
49809625cffSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
49909625cffSIan Rogers        "MSRValue": "0x1008000004",
50009625cffSIan Rogers        "SampleAfterValue": "100003",
50109625cffSIan Rogers        "UMask": "0x1"
50209625cffSIan Rogers    },
50309625cffSIan Rogers    {
50409625cffSIan Rogers        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
50509625cffSIan Rogers        "EventCode": "0xB7, 0xBB",
50609625cffSIan Rogers        "EventName": "OCR.DEMAND_CODE_RD.SNC_CACHE.HIT_WITH_FWD",
50709625cffSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
50809625cffSIan Rogers        "MSRValue": "0x808000004",
50909625cffSIan Rogers        "SampleAfterValue": "100003",
51009625cffSIan Rogers        "UMask": "0x1"
51109625cffSIan Rogers    },
51209625cffSIan Rogers    {
513f25db21bSIan Rogers        "BriefDescription": "Counts demand data reads that hit in the L3 or were snooped from another core's caches on the same socket.",
514f25db21bSIan Rogers        "EventCode": "0xB7, 0xBB",
515f25db21bSIan Rogers        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT",
516f25db21bSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
517f25db21bSIan Rogers        "MSRValue": "0x3F803C0001",
518f25db21bSIan Rogers        "SampleAfterValue": "100003",
519f25db21bSIan Rogers        "UMask": "0x1"
520f25db21bSIan Rogers    },
521f25db21bSIan Rogers    {
522f25db21bSIan Rogers        "BriefDescription": "Counts demand data reads that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
523f25db21bSIan Rogers        "EventCode": "0xB7, 0xBB",
524f25db21bSIan Rogers        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
525f25db21bSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
526f25db21bSIan Rogers        "MSRValue": "0x10003C0001",
527f25db21bSIan Rogers        "SampleAfterValue": "100003",
528f25db21bSIan Rogers        "UMask": "0x1"
529f25db21bSIan Rogers    },
530f25db21bSIan Rogers    {
531f25db21bSIan Rogers        "BriefDescription": "Counts demand data reads that resulted in a snoop that hit in another core, which did not forward the data.",
532f25db21bSIan Rogers        "EventCode": "0xB7, 0xBB",
533f25db21bSIan Rogers        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_NO_FWD",
534f25db21bSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
535f25db21bSIan Rogers        "MSRValue": "0x4003C0001",
536f25db21bSIan Rogers        "SampleAfterValue": "100003",
537f25db21bSIan Rogers        "UMask": "0x1"
538f25db21bSIan Rogers    },
539f25db21bSIan Rogers    {
540f25db21bSIan Rogers        "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
541f25db21bSIan Rogers        "EventCode": "0xB7, 0xBB",
542f25db21bSIan Rogers        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
543f25db21bSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
544f25db21bSIan Rogers        "MSRValue": "0x8003C0001",
545f25db21bSIan Rogers        "SampleAfterValue": "100003",
546f25db21bSIan Rogers        "UMask": "0x1"
547f25db21bSIan Rogers    },
548f25db21bSIan Rogers    {
54909625cffSIan Rogers        "BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.",
55009625cffSIan Rogers        "EventCode": "0xB7, 0xBB",
55109625cffSIan Rogers        "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HITM",
55209625cffSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
55309625cffSIan Rogers        "MSRValue": "0x1030000001",
55409625cffSIan Rogers        "SampleAfterValue": "100003",
55509625cffSIan Rogers        "UMask": "0x1"
55609625cffSIan Rogers    },
55709625cffSIan Rogers    {
55809625cffSIan Rogers        "BriefDescription": "Counts demand data reads that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
55909625cffSIan Rogers        "EventCode": "0xB7, 0xBB",
56009625cffSIan Rogers        "EventName": "OCR.DEMAND_DATA_RD.REMOTE_CACHE.SNOOP_HIT_WITH_FWD",
56109625cffSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
56209625cffSIan Rogers        "MSRValue": "0x830000001",
56309625cffSIan Rogers        "SampleAfterValue": "100003",
56409625cffSIan Rogers        "UMask": "0x1"
56509625cffSIan Rogers    },
56609625cffSIan Rogers    {
56709625cffSIan Rogers        "BriefDescription": "Counts demand data reads that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
56809625cffSIan Rogers        "EventCode": "0xB7, 0xBB",
56909625cffSIan Rogers        "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HITM",
57009625cffSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
57109625cffSIan Rogers        "MSRValue": "0x1008000001",
57209625cffSIan Rogers        "SampleAfterValue": "100003",
57309625cffSIan Rogers        "UMask": "0x1"
57409625cffSIan Rogers    },
57509625cffSIan Rogers    {
57609625cffSIan Rogers        "BriefDescription": "Counts demand data reads that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
57709625cffSIan Rogers        "EventCode": "0xB7, 0xBB",
57809625cffSIan Rogers        "EventName": "OCR.DEMAND_DATA_RD.SNC_CACHE.HIT_WITH_FWD",
57909625cffSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
58009625cffSIan Rogers        "MSRValue": "0x808000001",
58109625cffSIan Rogers        "SampleAfterValue": "100003",
58209625cffSIan Rogers        "UMask": "0x1"
58309625cffSIan Rogers    },
58409625cffSIan Rogers    {
585f25db21bSIan Rogers        "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.",
586f25db21bSIan Rogers        "EventCode": "0xB7, 0xBB",
587f25db21bSIan Rogers        "EventName": "OCR.DEMAND_RFO.L3_HIT",
588f25db21bSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
589f25db21bSIan Rogers        "MSRValue": "0x3F803C0002",
590f25db21bSIan Rogers        "SampleAfterValue": "100003",
591f25db21bSIan Rogers        "UMask": "0x1"
592f25db21bSIan Rogers    },
593f25db21bSIan Rogers    {
594f25db21bSIan Rogers        "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
595f25db21bSIan Rogers        "EventCode": "0xB7, 0xBB",
596f25db21bSIan Rogers        "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
597f25db21bSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
598f25db21bSIan Rogers        "MSRValue": "0x10003C0002",
599f25db21bSIan Rogers        "SampleAfterValue": "100003",
600f25db21bSIan Rogers        "UMask": "0x1"
601f25db21bSIan Rogers    },
602f25db21bSIan Rogers    {
60309625cffSIan Rogers        "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
60409625cffSIan Rogers        "EventCode": "0xB7, 0xBB",
60509625cffSIan Rogers        "EventName": "OCR.DEMAND_RFO.SNC_CACHE.HITM",
60609625cffSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
60709625cffSIan Rogers        "MSRValue": "0x1008000002",
60809625cffSIan Rogers        "SampleAfterValue": "100003",
60909625cffSIan Rogers        "UMask": "0x1"
61009625cffSIan Rogers    },
61109625cffSIan Rogers    {
61209625cffSIan Rogers        "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
61309625cffSIan Rogers        "EventCode": "0xB7, 0xBB",
61409625cffSIan Rogers        "EventName": "OCR.DEMAND_RFO.SNC_CACHE.HIT_WITH_FWD",
61509625cffSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
61609625cffSIan Rogers        "MSRValue": "0x808000002",
61709625cffSIan Rogers        "SampleAfterValue": "100003",
61809625cffSIan Rogers        "UMask": "0x1"
61909625cffSIan Rogers    },
62009625cffSIan Rogers    {
621f25db21bSIan Rogers        "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that hit in the L3 or were snooped from another core's caches on the same socket.",
622f25db21bSIan Rogers        "EventCode": "0xB7, 0xBB",
623f25db21bSIan Rogers        "EventName": "OCR.HWPF_L1D_AND_SWPF.L3_HIT",
624f25db21bSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
625f25db21bSIan Rogers        "MSRValue": "0x3F803C0400",
626f25db21bSIan Rogers        "SampleAfterValue": "100003",
627f25db21bSIan Rogers        "UMask": "0x1"
628f25db21bSIan Rogers    },
629f25db21bSIan Rogers    {
630f25db21bSIan Rogers        "BriefDescription": "Counts hardware prefetches to the L3 only that hit in the L3 or were snooped from another core's caches on the same socket.",
631f25db21bSIan Rogers        "EventCode": "0xB7, 0xBB",
632f25db21bSIan Rogers        "EventName": "OCR.HWPF_L3.L3_HIT",
633f25db21bSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
634f25db21bSIan Rogers        "MSRValue": "0x80082380",
635f25db21bSIan Rogers        "SampleAfterValue": "100003",
636f25db21bSIan Rogers        "UMask": "0x1"
637f25db21bSIan Rogers    },
638f25db21bSIan Rogers    {
639f25db21bSIan Rogers        "BriefDescription": "Counts hardware and software prefetches to all cache levels that hit in the L3 or were snooped from another core's caches on the same socket.",
640f25db21bSIan Rogers        "EventCode": "0xB7, 0xBB",
641f25db21bSIan Rogers        "EventName": "OCR.PREFETCHES.L3_HIT",
642f25db21bSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
643f25db21bSIan Rogers        "MSRValue": "0x3F803C27F0",
644f25db21bSIan Rogers        "SampleAfterValue": "100003",
645f25db21bSIan Rogers        "UMask": "0x1"
646f25db21bSIan Rogers    },
647f25db21bSIan Rogers    {
648d214d0c2SIan Rogers        "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit in the L3 or were snooped from another core's caches on the same socket.",
649f25db21bSIan Rogers        "EventCode": "0xB7, 0xBB",
650f25db21bSIan Rogers        "EventName": "OCR.READS_TO_CORE.L3_HIT",
651f25db21bSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
652f25db21bSIan Rogers        "MSRValue": "0x3F003C0477",
653f25db21bSIan Rogers        "SampleAfterValue": "100003",
654f25db21bSIan Rogers        "UMask": "0x1"
655f25db21bSIan Rogers    },
656f25db21bSIan Rogers    {
657d214d0c2SIan Rogers        "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit a modified line in another core's caches which forwarded the data.",
658f25db21bSIan Rogers        "EventCode": "0xB7, 0xBB",
659f25db21bSIan Rogers        "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HITM",
660f25db21bSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
661f25db21bSIan Rogers        "MSRValue": "0x10003C0477",
662f25db21bSIan Rogers        "SampleAfterValue": "100003",
663f25db21bSIan Rogers        "UMask": "0x1"
664f25db21bSIan Rogers    },
665f25db21bSIan Rogers    {
666d214d0c2SIan Rogers        "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop that hit in another core, which did not forward the data.",
667f25db21bSIan Rogers        "EventCode": "0xB7, 0xBB",
668f25db21bSIan Rogers        "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_NO_FWD",
669f25db21bSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
670f25db21bSIan Rogers        "MSRValue": "0x4003C0477",
671f25db21bSIan Rogers        "SampleAfterValue": "100003",
672f25db21bSIan Rogers        "UMask": "0x1"
673f25db21bSIan Rogers    },
674f25db21bSIan Rogers    {
675d214d0c2SIan Rogers        "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that resulted in a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
676f25db21bSIan Rogers        "EventCode": "0xB7, 0xBB",
677f25db21bSIan Rogers        "EventName": "OCR.READS_TO_CORE.L3_HIT.SNOOP_HIT_WITH_FWD",
678f25db21bSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
679f25db21bSIan Rogers        "MSRValue": "0x8003C0477",
680f25db21bSIan Rogers        "SampleAfterValue": "100003",
681f25db21bSIan Rogers        "UMask": "0x1"
682f25db21bSIan Rogers    },
683f25db21bSIan Rogers    {
684d214d0c2SIan Rogers        "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop was sent and data was returned (Modified or Not Modified).",
685f25db21bSIan Rogers        "EventCode": "0xB7, 0xBB",
686f25db21bSIan Rogers        "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_FWD",
687f25db21bSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
688f25db21bSIan Rogers        "MSRValue": "0x1830000477",
689f25db21bSIan Rogers        "SampleAfterValue": "100003",
690f25db21bSIan Rogers        "UMask": "0x1"
691f25db21bSIan Rogers    },
692f25db21bSIan Rogers    {
693d214d0c2SIan Rogers        "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit a modified line in another core's caches which forwarded the data.",
69409625cffSIan Rogers        "EventCode": "0xB7, 0xBB",
69509625cffSIan Rogers        "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM",
69609625cffSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
69709625cffSIan Rogers        "MSRValue": "0x1030000477",
69809625cffSIan Rogers        "SampleAfterValue": "100003",
69909625cffSIan Rogers        "UMask": "0x1"
70009625cffSIan Rogers    },
70109625cffSIan Rogers    {
702d214d0c2SIan Rogers        "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by a cache on a remote socket where a snoop hit in another core's caches which forwarded the unmodified data to the requesting core.",
70309625cffSIan Rogers        "EventCode": "0xB7, 0xBB",
70409625cffSIan Rogers        "EventName": "OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD",
70509625cffSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
70609625cffSIan Rogers        "MSRValue": "0x830000477",
70709625cffSIan Rogers        "SampleAfterValue": "100003",
70809625cffSIan Rogers        "UMask": "0x1"
70909625cffSIan Rogers    },
71009625cffSIan Rogers    {
711d214d0c2SIan Rogers        "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that hit a modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
71209625cffSIan Rogers        "EventCode": "0xB7, 0xBB",
71309625cffSIan Rogers        "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HITM",
71409625cffSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
71509625cffSIan Rogers        "MSRValue": "0x1008000477",
71609625cffSIan Rogers        "SampleAfterValue": "100003",
71709625cffSIan Rogers        "UMask": "0x1"
71809625cffSIan Rogers    },
71909625cffSIan Rogers    {
720d214d0c2SIan Rogers        "BriefDescription": "Counts all (cacheable) data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that either hit a non-modified line in a distant L3 Cache or were snooped from a distant core's L1/L2 caches on this socket when the system is in SNC (sub-NUMA cluster) mode.",
72109625cffSIan Rogers        "EventCode": "0xB7, 0xBB",
72209625cffSIan Rogers        "EventName": "OCR.READS_TO_CORE.SNC_CACHE.HIT_WITH_FWD",
72309625cffSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
72409625cffSIan Rogers        "MSRValue": "0x808000477",
72509625cffSIan Rogers        "SampleAfterValue": "100003",
72609625cffSIan Rogers        "UMask": "0x1"
72709625cffSIan Rogers    },
72809625cffSIan Rogers    {
729f25db21bSIan Rogers        "BriefDescription": "Counts streaming stores that hit in the L3 or were snooped from another core's caches on the same socket.",
730f25db21bSIan Rogers        "EventCode": "0xB7, 0xBB",
731f25db21bSIan Rogers        "EventName": "OCR.STREAMING_WR.L3_HIT",
732f25db21bSIan Rogers        "MSRIndex": "0x1a6,0x1a7",
733f25db21bSIan Rogers        "MSRValue": "0x80080800",
734f25db21bSIan Rogers        "SampleAfterValue": "100003",
735f25db21bSIan Rogers        "UMask": "0x1"
736f25db21bSIan Rogers    },
737f25db21bSIan Rogers    {
73809625cffSIan Rogers        "BriefDescription": "Demand and prefetch data reads",
73909625cffSIan Rogers        "EventCode": "0xB0",
74009625cffSIan Rogers        "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
74109625cffSIan Rogers        "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
74209625cffSIan Rogers        "SampleAfterValue": "100003",
74309625cffSIan Rogers        "UMask": "0x8"
74409625cffSIan Rogers    },
74509625cffSIan Rogers    {
74609625cffSIan Rogers        "BriefDescription": "Counts memory transactions sent to the uncore.",
74709625cffSIan Rogers        "EventCode": "0xB0",
74809625cffSIan Rogers        "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
74909625cffSIan Rogers        "PublicDescription": "Counts memory transactions sent to the uncore including requests initiated by the core, all L3 prefetches, reads resulting from page walks, and snoop responses.",
75009625cffSIan Rogers        "SampleAfterValue": "100003",
75109625cffSIan Rogers        "UMask": "0x80"
75209625cffSIan Rogers    },
75309625cffSIan Rogers    {
75409625cffSIan Rogers        "BriefDescription": "Counts cacheable and non-cacheable code reads to the core.",
75509625cffSIan Rogers        "EventCode": "0xb0",
75609625cffSIan Rogers        "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
75709625cffSIan Rogers        "PublicDescription": "Counts both cacheable and non-cacheable code reads to the core.",
75809625cffSIan Rogers        "SampleAfterValue": "100003",
75909625cffSIan Rogers        "UMask": "0x2"
76009625cffSIan Rogers    },
76109625cffSIan Rogers    {
76209625cffSIan Rogers        "BriefDescription": "Demand Data Read requests sent to uncore",
76309625cffSIan Rogers        "EventCode": "0xb0",
76409625cffSIan Rogers        "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
76509625cffSIan Rogers        "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
76609625cffSIan Rogers        "SampleAfterValue": "100003",
767cdb29a8fSJin Yao        "UMask": "0x1"
768cdb29a8fSJin Yao    },
769cdb29a8fSJin Yao    {
77009625cffSIan Rogers        "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
77109625cffSIan Rogers        "EventCode": "0xb0",
77209625cffSIan Rogers        "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
77309625cffSIan Rogers        "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
77409625cffSIan Rogers        "SampleAfterValue": "100003",
77509625cffSIan Rogers        "UMask": "0x4"
77609625cffSIan Rogers    },
77709625cffSIan Rogers    {
77809625cffSIan Rogers        "BriefDescription": "For every cycle, increments by the number of outstanding data read requests pending.",
77909625cffSIan Rogers        "EventCode": "0x60",
78009625cffSIan Rogers        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
78109625cffSIan Rogers        "PublicDescription": "For every cycle, increments by the number of outstanding data read requests pending.  Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3.  Reads due to page walks resulting from any request type will also be counted.  Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
78209625cffSIan Rogers        "SampleAfterValue": "1000003",
78309625cffSIan Rogers        "UMask": "0x8"
78409625cffSIan Rogers    },
78509625cffSIan Rogers    {
78609625cffSIan Rogers        "BriefDescription": "Cycles where at least 1 outstanding data read request is pending.",
78709625cffSIan Rogers        "CounterMask": "1",
78809625cffSIan Rogers        "EventCode": "0x60",
78909625cffSIan Rogers        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
79009625cffSIan Rogers        "PublicDescription": "Cycles where at least 1 outstanding data read request is pending.  Data read requests include cacheable demand reads and L2 prefetches, but do not include RFOs, code reads or prefetches to the L3.  Reads due to page walks resulting from any request type will also be counted.  Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
79109625cffSIan Rogers        "SampleAfterValue": "1000003",
79209625cffSIan Rogers        "UMask": "0x8"
79309625cffSIan Rogers    },
79409625cffSIan Rogers    {
79509625cffSIan Rogers        "BriefDescription": "Cycles with outstanding code read requests pending.",
79609625cffSIan Rogers        "CounterMask": "1",
79709625cffSIan Rogers        "EventCode": "0x60",
79809625cffSIan Rogers        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
79909625cffSIan Rogers        "PublicDescription": "Cycles with outstanding code read requests pending.  Code Read requests include both cacheable and non-cacheable Code Reads.  Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
80009625cffSIan Rogers        "SampleAfterValue": "1000003",
801cdb29a8fSJin Yao        "UMask": "0x2"
802cdb29a8fSJin Yao    },
803cdb29a8fSJin Yao    {
80409625cffSIan Rogers        "BriefDescription": "Cycles where at least 1 outstanding Demand RFO request is pending.",
80509625cffSIan Rogers        "CounterMask": "1",
80609625cffSIan Rogers        "EventCode": "0x60",
80709625cffSIan Rogers        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
80809625cffSIan Rogers        "PublicDescription": "Cycles where at least 1 outstanding Demand RFO request is pending.   RFOs are initiated by a core as part of a data store operation.  Demand RFO requests include RFOs, locks, and ItoM transactions.  Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
80909625cffSIan Rogers        "SampleAfterValue": "1000003",
81009625cffSIan Rogers        "UMask": "0x4"
81109625cffSIan Rogers    },
81209625cffSIan Rogers    {
81309625cffSIan Rogers        "BriefDescription": "For every cycle, increments by the number of outstanding code read requests pending.",
81409625cffSIan Rogers        "EventCode": "0x60",
81509625cffSIan Rogers        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
81609625cffSIan Rogers        "PublicDescription": "For every cycle, increments by the number of outstanding code read requests pending.  Code Read requests include both cacheable and non-cacheable Code Reads.   Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
81709625cffSIan Rogers        "SampleAfterValue": "1000003",
81809625cffSIan Rogers        "UMask": "0x2"
81909625cffSIan Rogers    },
82009625cffSIan Rogers    {
82109625cffSIan Rogers        "BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.",
82209625cffSIan Rogers        "EventCode": "0x60",
82309625cffSIan Rogers        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
82409625cffSIan Rogers        "PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.   Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
82509625cffSIan Rogers        "SampleAfterValue": "1000003",
82609625cffSIan Rogers        "UMask": "0x1"
82709625cffSIan Rogers    },
82809625cffSIan Rogers    {
829*0ec73817SIan Rogers        "BriefDescription": "Counts bus locks, accounts for cache line split locks and UC locks.",
830*0ec73817SIan Rogers        "EventCode": "0xF4",
831*0ec73817SIan Rogers        "EventName": "SQ_MISC.BUS_LOCK",
832*0ec73817SIan Rogers        "PublicDescription": "Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically.  Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory.",
833*0ec73817SIan Rogers        "SampleAfterValue": "100003",
834*0ec73817SIan Rogers        "UMask": "0x10"
835*0ec73817SIan Rogers    },
836*0ec73817SIan Rogers    {
837cdb29a8fSJin Yao        "BriefDescription": "Cycles the queue waiting for offcore responses is full.",
838cdb29a8fSJin Yao        "EventCode": "0xf4",
839cdb29a8fSJin Yao        "EventName": "SQ_MISC.SQ_FULL",
840cdb29a8fSJin Yao        "PublicDescription": "Counts the cycles for which the thread is active and the queue waiting for responses from the uncore cannot take any more entries.",
841cdb29a8fSJin Yao        "SampleAfterValue": "100003",
842cdb29a8fSJin Yao        "UMask": "0x4"
843f25db21bSIan Rogers    },
844f25db21bSIan Rogers    {
845f25db21bSIan Rogers        "BriefDescription": "Number of PREFETCHNTA instructions executed.",
846f25db21bSIan Rogers        "EventCode": "0x32",
847f25db21bSIan Rogers        "EventName": "SW_PREFETCH_ACCESS.NTA",
848f25db21bSIan Rogers        "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
849f25db21bSIan Rogers        "SampleAfterValue": "100003",
850f25db21bSIan Rogers        "UMask": "0x1"
851f25db21bSIan Rogers    },
852f25db21bSIan Rogers    {
853f25db21bSIan Rogers        "BriefDescription": "Number of PREFETCHW instructions executed.",
854f25db21bSIan Rogers        "EventCode": "0x32",
855f25db21bSIan Rogers        "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
856f25db21bSIan Rogers        "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
857f25db21bSIan Rogers        "SampleAfterValue": "100003",
858f25db21bSIan Rogers        "UMask": "0x8"
859f25db21bSIan Rogers    },
860f25db21bSIan Rogers    {
861f25db21bSIan Rogers        "BriefDescription": "Number of PREFETCHT0 instructions executed.",
862f25db21bSIan Rogers        "EventCode": "0x32",
863f25db21bSIan Rogers        "EventName": "SW_PREFETCH_ACCESS.T0",
864f25db21bSIan Rogers        "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
865f25db21bSIan Rogers        "SampleAfterValue": "100003",
866f25db21bSIan Rogers        "UMask": "0x2"
867f25db21bSIan Rogers    },
868f25db21bSIan Rogers    {
869f25db21bSIan Rogers        "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
870f25db21bSIan Rogers        "EventCode": "0x32",
871f25db21bSIan Rogers        "EventName": "SW_PREFETCH_ACCESS.T1_T2",
872f25db21bSIan Rogers        "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
873f25db21bSIan Rogers        "SampleAfterValue": "100003",
874f25db21bSIan Rogers        "UMask": "0x4"
875cdb29a8fSJin Yao    }
876cdb29a8fSJin Yao]
877