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/openbmc/linux/Documentation/devicetree/bindings/mux/
H A Dmux-consumer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/mux-consumer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Rosin <peda@axentia.se>
13 Mux controller consumers should specify a list of mux controllers that they
14 want to use with a property containing a 'mux-ctrl-list':
16 mux-ctrl-list ::= <single-mux-ctrl> [mux-ctrl-list]
17 single-mux-ctrl ::= <mux-ctrl-phandle> [mux-ctrl-specifier]
18 mux-ctrl-phandle : phandle to mux controller node
[all …]
H A Dreg-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/reg-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Generic register bitfield-based multiplexer controller
10 - Peter Rosin <peda@axentia.se>
19 - reg-mux # parent device of mux controller is not syscon device
20 - mmio-mux # parent device of mux controller is syscon device
24 '#mux-control-cells':
27 mux-reg-masks:
[all …]
H A Dadi,adg792a.txt4 - compatible : "adi,adg792a" or "adi,adg792g"
5 - #mux-control-cells : <0> if parallel (the three muxes are bound together
6 with a single mux controller controlling all three muxes), or <1> if
7 not (one mux controller for each mux).
8 * Standard mux-controller bindings as described in mux-controller.yaml
11 - gpio-controller : if present, #gpio-cells below is required.
12 - #gpio-cells : should be <2>
13 - First cell is the GPO line number, i.e. 0 or 1
14 - Second cell is used to specify active high (0)
18 - idle-state : if present, array of states that the mux controllers will have
[all …]
H A Dgpio-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/gpio-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: GPIO-based multiplexer controller
10 - Peter Rosin <peda@axentia.se>
22 const: gpio-mux
24 mux-gpios:
28 '#mux-control-cells':
31 '#mux-state-cells':
[all …]
H A Dmux-controller.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mux/mux-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Rosin <peda@axentia.se>
13 A multiplexer (or mux) controller will have one, or several, consumer devices
14 that uses the mux controller. Thus, a mux controller can possibly control
16 multiplexer needed by each consumer, but a single mux controller can of course
19 A mux controller provides a number of states to its consumers, and the state
20 space is a simple zero-based enumeration. I.e. 0-1 for a 2-way multiplexer,
[all …]
H A Dadi,adgs1408.txt1 Bindings for Analog Devices ADGS1408/1409 8:1/Dual 4:1 Mux
4 - compatible : Should be one of
7 * Standard mux-controller bindings as described in mux-controller.yaml
10 - gpio-controller : if present, #gpio-cells is required.
11 - #gpio-cells : should be <2>
12 - First cell is the GPO line number, i.e. 0 to 3
14 - Second cell is used to specify active high (0)
18 - idle-state : if present, the state that the mux controller will have
28 * One mux controller.
29 * Mux state set to idle as is (no idle-state declared)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmdio-mux-multiplexer.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-multiplexer.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of MDIO mux when MDIO mux is defined as a consumer
14 of a mux producer device. The mux producer can be of any type like mmio mux
15 producer, gpio mux producer or generic register based mux producer.
19 - $ref: /schemas/net/mdio-mux.yaml#
23 const: mdio-mux-multiplexer
[all …]
H A Dmdio-mux-mmioreg.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Properties for an MDIO bus multiplexer controlled by a memory-mapped device
10 - Andrew Lunn <andrew@lunn.ch>
13 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
14 like an FPGA, is used to control which child bus is connected. The mdio-mux
15 node must be a child of the memory-mapped device. The driver currently only
16 supports devices with 8, 16 or 32-bit registers.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/multiplexer/
H A Dio-channel-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/iio/multiplexer/io-channel-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Rosin <peda@axentia.se>
16 For each non-empty string in the channels property, an io-channel will be
17 created. The number of this io-channel is the same as the index into the list
18 of strings in the channels property, and also matches the mux controller
19 state. The mux controller state is described in
20 Documentation/devicetree/bindings/mux/mux-controller.yaml
[all …]
/openbmc/linux/arch/arm/boot/dts/aspeed/
H A Daspeed-bmc-ampere-mtjade.dts1 // SPDX-License-Identifier: GPL-2.0+
2 /dts-v1/;
3 #include "aspeed-g5.dtsi"
4 #include <dt-bindings/gpio/aspeed-gpio.h>
8 compatible = "ampere,mtjade-bmc", "aspeed,ast2500";
12 * i2c bus 50-57 assigned to NVMe slot 0-7
24 * i2c bus 60-67 assigned to NVMe slot 8-15
36 * i2c bus 70-77 assigned to NVMe slot 16-23
48 * i2c bus 80-81 assigned to NVMe M2 slot 0-1
60 stdout-path = &uart5;
[all …]
H A Daspeed-bmc-ampere-mtmitchell.dts1 // SPDX-License-Identifier: GPL-2.0-only
4 /dts-v1/;
6 #include "aspeed-g6.dtsi"
7 #include <dt-bindings/i2c/i2c.h>
8 #include <dt-bindings/gpio/aspeed-gpio.h>
12 compatible = "ampere,mtmitchell-bmc", "aspeed,ast2600";
27 * i2c bus 30-31 assigned to OCP slot 0-1
33 * i2c bus 32-33 assigned to Riser slot 0-1
39 * i2c bus 38-39 assigned to FRU on Riser slot 0-1
82 stdout-path = &uart5;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/media/
H A Dvideo-mux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/media/video-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sakari Ailus <sakari.ailus@linux.intel.com>
11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
20 const: video-mux
22 mux-controls:
25 '#address-cells':
28 '#size-cells':
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91-natte.dtsi1 // SPDX-License-Identifier: GPL-2.0+
3 * at91-natte.dts - Device Tree include file for the Natte board
11 mux: mux-controller { label
12 compatible = "gpio-mux";
13 #mux-control-cells = <0>;
15 mux-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>,
20 batntc-mux {
21 compatible = "io-channel-mux";
22 io-channels = <&adc 5>;
23 io-channel-names = "parent";
[all …]
/openbmc/linux/Documentation/devicetree/bindings/i2c/
H A Di2c-mux-gpmux.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-mux-gpmux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: General Purpose I2C Bus Mux
10 - Peter Rosin <peda@axentia.se>
13 This binding describes an I2C bus multiplexer that uses a mux controller
14 from the mux subsystem to route the I2C signals.
16 .-----. .-----.
18 .------------. '-----' '-----'
[all …]
/openbmc/linux/Documentation/devicetree/bindings/spi/
H A Dspi-mux.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/spi/spi-mux.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
13 setting of the multiplexer to a channel needs to be done by a specific SPI mux
16 MOSI /--------------------------------+--------+--------+--------\
17 MISO |/------------------------------+|-------+|-------+|-------\|
18 SCL ||/----------------------------+||------+||------+||------\||
20 +------------+ ||| ||| ||| |||
21 | SoC ||| | +-+++-+ +-+++-+ +-+++-+ +-+++-+
[all …]
/openbmc/linux/include/dt-bindings/clock/
H A Dtegra186-clock.h1 /* SPDX-License-Identifier: GPL-2.0 */
384 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
386 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
388 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */
392 /** @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */
394 /** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */
396 /** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */
398 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */
400 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */
402 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */
[all …]
/openbmc/u-boot/include/dt-bindings/clock/
H A Dtegra186-clock.h383 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
385 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
387 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */
391 /** @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */
393 /** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */
395 /** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */
397 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */
399 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */
401 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */
403 /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */
[all …]
/openbmc/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5_pcb125.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
11 compatible = "microchip,sparx5-pcb125", "microchip,sparx5";
20 emmc_pins: emmc-pins {
28 drive-strength = <3>;
35 bus-width = <8>;
36 non-removable;
37 pinctrl-0 = <&emmc_pins>;
38 max-frequency = <8000000>;
39 microchip,clock-delay = <10>;
[all …]
/openbmc/linux/Documentation/devicetree/bindings/display/bridge/
H A Dnwl-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Northwest Logic MIPI-DSI controller on i.MX SoCs
10 - Guido Gúnther <agx@sigxcpu.org>
11 - Robert Chiras <robert.chiras@nxp.com>
14 NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
15 the SOCs NWL MIPI-DSI host controller.
18 - $ref: ../dsi-controller.yaml#
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dti,phy-am654-serdes.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/ti,phy-am654-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
14 - Kishon Vijay Abraham I <kishon@ti.com>
19 - ti,phy-am654-serdes
24 reg-names:
26 - const: serdes
28 power-domains:
37 '#phy-cells':
[all …]
/openbmc/linux/Documentation/admin-guide/media/
H A Dimx7.rst1 .. SPDX-License-Identifier: GPL-2.0
7 ------------
14 - CMOS Sensor Interface (CSI)
15 - Video Multiplexer
16 - MIPI CSI-2 Receiver
18 .. code-block:: none
20 MIPI Camera Input ---> MIPI CSI-2 --- > |\
24 | U | ------> CSI ---> Capture
27 Parallel Camera Input ----------------> | /
34 --------
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dwm8770.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * wm8770.c -- WM8770 ALSA SoC Audio driver
105 regcache_mark_dirty(wm8770->regmap); \
114 static const DECLARE_TLV_DB_SCALE(adc_tlv, -1200, 100, 0);
115 static const DECLARE_TLV_DB_SCALE(dac_dig_tlv, -12750, 50, 1);
116 static const DECLARE_TLV_DB_SCALE(dac_alg_tlv, -12700, 100, 1);
133 /* global DAC playback controls */
139 /* global VOUT playback controls */
144 /* VOUT1/2/3/4 specific controls */
162 /* DAC1/2/3/4 specific controls */
[all …]
H A Dda7213.c1 // SPDX-License-Identifier: GPL-2.0-or-later
33 /* -54dB */
34 0x0, 0x11, TLV_DB_SCALE_ITEM(-5400, 0, 0),
35 /* -52.5dB to 15dB */
36 0x12, 0x3f, TLV_DB_SCALE_ITEM(-5250, 150, 0)
41 /* -78dB to 12dB */
42 0x08, 0x7f, TLV_DB_SCALE_ITEM(-7800, 75, 0)
51 static const DECLARE_TLV_DB_SCALE(mic_vol_tlv, -600, 600, 0);
52 static const DECLARE_TLV_DB_SCALE(mixin_gain_tlv, -450, 150, 0);
53 static const DECLARE_TLV_DB_SCALE(eq_gain_tlv, -1050, 150, 0);
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra-pinmux-common.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra-pinmux-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
14 Please refer to pinctrl-bindings.txt in this directory for details of the
21 include the mux function to select on those pin(s)/ group(s), and various
22 pin configuration parameters, such as pull-up, tristate, drive strength,
29 other words, a subnode that lists a mux function but no pin configuration
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mtd/
H A Dti,am654-hbmc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/ti,am654-hbmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vignesh Raghavendra <vigneshr@ti.com>
14 const: ti,am654-hbmc
19 power-domains: true
20 '#address-cells': true
21 '#size-cells': true
24 mux-controls:
[all …]

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