1*652f2efaSRob Herring# SPDX-License-Identifier: GPL-2.0 2*652f2efaSRob Herring%YAML 1.2 3*652f2efaSRob Herring--- 4*652f2efaSRob Herring$id: http://devicetree.org/schemas/net/mdio-mux-mmioreg.yaml# 5*652f2efaSRob Herring$schema: http://devicetree.org/meta-schemas/core.yaml# 6*652f2efaSRob Herring 7*652f2efaSRob Herringtitle: Properties for an MDIO bus multiplexer controlled by a memory-mapped device 8*652f2efaSRob Herring 9*652f2efaSRob Herringmaintainers: 10*652f2efaSRob Herring - Andrew Lunn <andrew@lunn.ch> 11*652f2efaSRob Herring 12*652f2efaSRob Herringdescription: |+ 13*652f2efaSRob Herring This is a special case of a MDIO bus multiplexer. A memory-mapped device, 14*652f2efaSRob Herring like an FPGA, is used to control which child bus is connected. The mdio-mux 15*652f2efaSRob Herring node must be a child of the memory-mapped device. The driver currently only 16*652f2efaSRob Herring supports devices with 8, 16 or 32-bit registers. 17*652f2efaSRob Herring 18*652f2efaSRob HerringallOf: 19*652f2efaSRob Herring - $ref: /schemas/net/mdio-mux.yaml# 20*652f2efaSRob Herring 21*652f2efaSRob Herringproperties: 22*652f2efaSRob Herring compatible: 23*652f2efaSRob Herring items: 24*652f2efaSRob Herring - const: mdio-mux-mmioreg 25*652f2efaSRob Herring - const: mdio-mux 26*652f2efaSRob Herring 27*652f2efaSRob Herring reg: 28*652f2efaSRob Herring description: Contains the offset of the register that controls the bus 29*652f2efaSRob Herring multiplexer. The size field in the 'reg' property is the size of register, 30*652f2efaSRob Herring and must therefore be 1, 2, or 4. 31*652f2efaSRob Herring maxItems: 1 32*652f2efaSRob Herring 33*652f2efaSRob Herring mux-mask: 34*652f2efaSRob Herring $ref: /schemas/types.yaml#/definitions/uint32 35*652f2efaSRob Herring description: Contains an eight-bit mask that specifies which bits in the 36*652f2efaSRob Herring register control the actual bus multiplexer. The 'reg' property of each 37*652f2efaSRob Herring child mdio-mux node must be constrained by this mask. 38*652f2efaSRob Herring 39*652f2efaSRob Herringrequired: 40*652f2efaSRob Herring - compatible 41*652f2efaSRob Herring - reg 42*652f2efaSRob Herring - mux-mask 43*652f2efaSRob Herring 44*652f2efaSRob HerringunevaluatedProperties: false 45*652f2efaSRob Herring 46*652f2efaSRob Herringexamples: 47*652f2efaSRob Herring - | 48*652f2efaSRob Herring mdio-mux@9 { 49*652f2efaSRob Herring compatible = "mdio-mux-mmioreg", "mdio-mux"; 50*652f2efaSRob Herring mdio-parent-bus = <&xmdio0>; 51*652f2efaSRob Herring #address-cells = <1>; 52*652f2efaSRob Herring #size-cells = <0>; 53*652f2efaSRob Herring reg = <9 1>; // BRDCFG1 54*652f2efaSRob Herring mux-mask = <0x6>; // EMI2 55*652f2efaSRob Herring 56*652f2efaSRob Herring mdio@0 { // Slot 1 XAUI (FM2) 57*652f2efaSRob Herring reg = <0>; 58*652f2efaSRob Herring #address-cells = <1>; 59*652f2efaSRob Herring #size-cells = <0>; 60*652f2efaSRob Herring 61*652f2efaSRob Herring phy_xgmii_slot1: ethernet-phy@4 { 62*652f2efaSRob Herring compatible = "ethernet-phy-ieee802.3-c45"; 63*652f2efaSRob Herring reg = <4>; 64*652f2efaSRob Herring }; 65*652f2efaSRob Herring }; 66*652f2efaSRob Herring 67*652f2efaSRob Herring mdio@2 { // Slot 2 XAUI (FM1) 68*652f2efaSRob Herring reg = <2>; 69*652f2efaSRob Herring #address-cells = <1>; 70*652f2efaSRob Herring #size-cells = <0>; 71*652f2efaSRob Herring 72*652f2efaSRob Herring ethernet-phy@4 { 73*652f2efaSRob Herring compatible = "ethernet-phy-ieee802.3-c45"; 74*652f2efaSRob Herring reg = <4>; 75*652f2efaSRob Herring }; 76*652f2efaSRob Herring }; 77*652f2efaSRob Herring }; 78*652f2efaSRob Herring... 79