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/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dfsl,mu-msi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller
10 - Frank Li <Frank.Li@nxp.com>
15 and control) through the MU interface. The MU also provides the ability
16 for one processor (A side) to signal the other processor (B side) using
19 Because the MU manages the messaging between processors, the MU uses
20 different clocks (from each side of the different peripheral buses).
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/openbmc/linux/Documentation/devicetree/bindings/mailbox/
H A Dfsl,mu.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/fsl,mu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NXP i.MX Messaging Unit (MU)
10 - Dong Aisheng <aisheng.dong@nxp.com>
15 and control) through the MU interface. The MU also provides the ability
18 Because the MU manages the messaging between processors, the MU uses
19 different clocks (from each side of the different peripheral buses).
20 Therefore, the MU must synchronize the accesses from one side to the
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/openbmc/linux/drivers/irqchip/
H A Dirq-imx-mu-msi.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Freescale MU used as MSI controller
10 * Based on drivers/mailbox/imx-mailbox.c
50 #define IMX_MU_xCR_RIEn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
51 #define IMX_MU_xSR_RFn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
73 iowrite32(val, msi_data->regs + offs); in imx_mu_write()
78 return ioread32(msi_data->regs + offs); in imx_mu_read()
86 raw_spin_lock_irqsave(&msi_data->lock, flags); in imx_mu_xcr_rmw()
87 val = imx_mu_read(msi_data, msi_data->cfg->xCR[type]); in imx_mu_xcr_rmw()
90 imx_mu_write(msi_data, val, msi_data->cfg->xCR[type]); in imx_mu_xcr_rmw()
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/openbmc/linux/drivers/net/wireless/intel/iwlwifi/fw/api/
H A Ddatapath.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2022 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2016-2017 Intel Deutschland GmbH
11 * enum iwl_data_path_subcmd_ids - data path group commands
131 * struct iwl_mu_group_mgmt_cmd - VHT MU-MIMO group configuration
134 * @membership_status: a bitmap of MU groups
136 * group then bits (group * 2) is the position -1
145 * struct iwl_mu_group_mgmt_notif - VHT MU-MIMO group id notification
147 * @membership_status: a bitmap of MU groups
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H A Drx.h1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
3 * Copyright (C) 2012-2014, 2018-2022 Intel Corporation
4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH
5 * Copyright (C) 2015-2017 Intel Deutschland GmbH
10 /* API for pre-9000 hardware */
26 * struct iwl_rx_phy_info - phy info
34 * @beacon_time_stamp: beacon at on-air rise
39 * @byte_count: frame's byte-count
70 * bits 0:3 - reserved
71 * bits 4:7 - MIC CRC length
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/openbmc/linux/drivers/net/wireless/ath/ath11k/
H A Ddebugfs_htt_stats.h1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */
3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2022-2023 Qualcomm Innovation Center, Inc. All rights reserved.
253 * The histogram bins are 0-29, 30-59, 60-89 and so on. The are
465 /* element 0,1, ...7 -> NSS 1,2, ...8 */
473 * (400us, 800us, 1600us & 3200us) in each mcs (0-11)
501 /* element 0,1, ...7 -> NSS 1,2, ...8 */
512 /* Counters to track number of rx packets in each GI in each mcs (0-11) */
536 /* MU MIMO stats per hwQ */
595 /* histogram of ppdu post to hwsch - > cmd status received */
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/openbmc/linux/sound/pci/emu10k1/
H A Demu10k1_main.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * James Courtier-Dutton <James@superbug.co.uk>
85 if (emu->audigy) { in snd_emu10k1_voice_init()
128 { 0x0e, 0xcf }, /* Attenuation Left 0x01 = -103dB, 0xff = 24dB */
146 HCFG_MUTEBUTTONENABLE, emu->port + HCFG); in snd_emu10k1_init()
148 outl(0, emu->port + INTE); in snd_emu10k1_init()
169 if (emu->audigy) { in snd_emu10k1_init()
182 SPCS0, emu->spdif_bits[0], in snd_emu10k1_init()
183 SPCS1, emu->spdif_bits[1], in snd_emu10k1_init()
184 SPCS2, emu->spdif_bits[2], in snd_emu10k1_init()
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/openbmc/linux/drivers/mailbox/
H A Dimx-mailbox.c1 // SPDX-License-Identifier: GPL-2.0
24 /* TX0/RX0/RXDB[0-3] */
118 #define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
119 #define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
120 #define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
123 #define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
125 #define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
127 #define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
129 #define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
130 /* MU reset */
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/openbmc/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A Dother.json50 …dified (M) data from another core's ECO L3 on the same chip due to a data side request. When using…
65 "BriefDescription": "Read-write data cache collisions"
90 "BriefDescription": "D-cache invalidates sent over the reload bus to the core"
200 "BriefDescription": "Read-write data cache collisions"
280 …-word boundary, which causes it to require an additional slice than than what normally would be re…
300 "BriefDescription": "I-cache Invalidates sent over the realod bus to the core"
395 …-word boundary, which causes it to require an additional slice than than what normally would be re…
405 …"BriefDescription": "TM snoop that is a store hits line in L3 in M or Mu state (exclusive modified…
430 "BriefDescription": "TM Load (fav or non-fav) ran into conflict (failed)"
450 …"BriefDescription": "A TM-ineligible instruction tries to execute inside a transaction and the LSU…
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/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7s.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <1>;
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/openbmc/linux/drivers/remoteproc/
H A Dimx_rproc.c1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <dt-bindings/firmware/imx/rsrc.h>
7 #include <linux/arm-smccc.h>
74 * struct imx_rproc_mem - slim internal memory structure
124 /* TCM CODE NON-SECURE */
132 /* TCM SYS NON-SECURE*/
185 /* QSPI Code - alias */
187 /* DDR (Code) - alias */
191 /* OCRAM_S - alias */
205 /* TCML - alias */
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/openbmc/qemu/hw/usb/
H A Dquirks-ftdi-ids.h5 * Philipp Gühring - pg@futureware.at - added the Device ID of the USB relais
24 #define FTDI_4232H_PID 0x6011 /* Quad channel hi-speed device */
25 #define FTDI_232H_PID 0x6014 /* Single channel hi-speed device */
26 #define FTDI_FTX_PID 0x6015 /* FT-X series (FT201X, FT230X, FT231X, etc) */
31 /*** third-party PIDs (using FTDI_VID) ***/
37 * http://www.open-rd.org
64 /* FTDI 2332C Dual channel device, side A=245 FIFO (JTAG), Side B=RS232 UART */
69 #define FTDI_TURTELIZER_PID 0xBDC8 /* JTAG/RS-232 adapter by egnite GmbH */
79 #define FTDI_NZR_SEM_USB_PID 0xC1E0 /* NZR SEM-LOG16+ */
82 * RR-CirKits LocoBuffer USB (http://www.rr-cirkits.com)
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/openbmc/linux/drivers/usb/serial/
H A Dftdi_sio_ids.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Philipp Gühring - pg@futureware.at - added the Device ID of the USB relais
25 #define FTDI_4232H_PID 0x6011 /* Quad channel hi-speed device */
26 #define FTDI_232H_PID 0x6014 /* Single channel hi-speed device */
27 #define FTDI_FTX_PID 0x6015 /* FT-X series (FT201X, FT230X, FT231X, etc) */
28 #define FTDI_FT2233HP_PID 0x6040 /* Dual channel hi-speed device with PD */
29 #define FTDI_FT4233HP_PID 0x6041 /* Quad channel hi-speed device with PD */
30 #define FTDI_FT2232HP_PID 0x6042 /* Dual channel hi-speed device with PD */
31 #define FTDI_FT4232HP_PID 0x6043 /* Quad channel hi-speed device with PD */
32 #define FTDI_FT233HP_PID 0x6044 /* Dual channel hi-speed device with PD */
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/openbmc/linux/sound/usb/
H A Dmixer.c1 // SPDX-License-Identifier: GPL-2.0-or-later
17 * - support for UAC2 effect units
18 * - support for graphical equalizers
19 * - RANGE and MEM set commands (UAC2)
20 * - RANGE and MEM interrupt dispatchers (UAC2)
21 * - audio channel clustering (UAC2)
22 * - audio sample rate converter units (UAC2)
23 * - proper handling of clock multipliers (UAC2)
24 * - dispatch clock change notifications (UAC2)
25 * - stop PCM streams which use a clock that became invalid
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/openbmc/linux/drivers/net/wireless/ath/ath10k/
H A Dhtt.h1 /* SPDX-License-Identifier: ISC */
3 * Copyright (c) 2005-2011 Atheros Communications Inc.
4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
29 /* bits 5-23 currently reserved */
34 enum htt_h2t_msg_type { /* host-to-target */
57 u8 pad[sizeof(u32) - sizeof(struct htt_cmd_hdr)];
74 * but the host shall use the bit-mast + bit-shift defs, to be endian-
176 * htt_data_tx_desc - used for data tx path
179 * ext_tid: for qos-data frames (0-15), see %HTT_DATA_TX_EXT_TID_
241 #define HTT_RX_RING_FILL_LEVEL (((HTT_RX_RING_SIZE) / 2) - 1)
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/openbmc/linux/include/net/
H A Dmac80211.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * mac80211 <-> driver interface
5 * Copyright 2002-2005, Devicescape Software, Inc.
6 * Copyright 2006-2007 Jiri Benc <jbenc@suse.cz>
7 * Copyright 2007-2010 Johannes Berg <johannes@sipsolutions.net>
8 * Copyright 2013-2014 Intel Mobile Communications GmbH
9 * Copyright (C) 2015 - 2017 Intel Deutschland GmbH
10 * Copyright (C) 2018 - 2023 Intel Corporation
31 * only partial functionality in hard- or firmware. This document
32 * defines the interface between mac80211 and low-level hardware
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/openbmc/linux/net/mac80211/
H A Dmlme.c1 // SPDX-License-Identifier: GPL-2.0-only
4 * Copyright 2003-2008, Jouni Malinen <j@w1.fi>
7 * Copyright 2006-2007 Jiri Benc <jbenc@suse.cz>
9 * Copyright 2013-2014 Intel Mobile Communications GmbH
10 * Copyright (C) 2015 - 2017 Intel Deutschland GmbH
11 * Copyright (C) 2018 - 2023 Intel Corporation
29 #include "driver-ops.h"
100 struct ieee80211_eht_operation_info *info = (void *)eht_oper->optional; in ieee80211_extract_dis_subch_bmap()
107 if (!(eht_oper->params & IEEE80211_EHT_OPER_INFO_PRESENT) || in ieee80211_extract_dis_subch_bmap()
108 !(eht_oper->params & in ieee80211_extract_dis_subch_bmap()
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/openbmc/linux/drivers/net/wireless/ath/ath12k/
H A Dmac.c1 // SPDX-License-Identifier: BSD-3-Clause-Clear
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2023 Qualcomm Innovation Center, Inc. All rights reserved.
233 #define ath12k_a_rates_size (ARRAY_SIZE(ath12k_legacy_rates) - 4)
255 return "11b"; in ath12k_mac_phymode_str()
259 return "11na-ht20"; in ath12k_mac_phymode_str()
261 return "11ng-ht20"; in ath12k_mac_phymode_str()
263 return "11na-ht40"; in ath12k_mac_phymode_str()
265 return "11ng-ht40"; in ath12k_mac_phymode_str()
267 return "11ac-vht20"; in ath12k_mac_phymode_str()
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/openbmc/
Dopengrok1.0.log1 2025-03-15 03:00:37.236-0500 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler
2 2025-03-15 03:00:37.352-0500 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -
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Dopengrok2.0.log1 2025-03-14 03:00:40.378-0500 FINE t1 Executor.registerErrorHandler: Installing default uncaught exception handler
2 2025-03-14 03:00:40.496-0500 INFO t1 Indexer.parseOptions: Indexer options: [-c, /usr/local/bin/ctags, -T, 12, -s, /opengrok/src, -
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/openbmc/linux/
H A Dopengrok0.0.log1 2024-12-28 20:09:05.996-0600 FINEST t1171 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/linux/drivers/staging/media/av7110/video-continue.rst.gz'
2 2024-12-28 20:09:05.942-0600 FINEST t1149 PendingFileCompleter.doRename: Moved pending as file: '/opengrok/data/xref/openbmc/u-boot/arch/sh/config.mk.gz'
3 2024-12-2
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