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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dfsl,mxs-pinctrl.txt3 The pins controlled by mxs pin controller are organized in banks, each bank
4 has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th
5 function is GPIO. The configuration on the pins includes drive strength,
6 voltage and pull-up.
9 - compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl"
10 - reg: Should contain the register physical address and length for the
13 Please refer to pinctrl-bindings.txt in this directory for details of the
18 a group of pins, and only affects those parameters that are explicitly listed.
20 information about pull-up. For this reason, even seemingly boolean values are
26 One is to set up a group of pins for a function, both mux selection and pin
[all …]
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91-sama5d3_ksz9477_evb.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
5 /dts-v1/;
9 model = "EVB-KSZ9477";
10 compatible = "microchip,sama5d3-ksz9477-evb", "atmel,sama5d36",
14 stdout-path = &dbgu;
17 reg_3v3: regulator-3v3 {
18 compatible = "regulator-fixed";
19 regulator-name = "3v3";
20 regulator-min-microvolt = <3300000>;
21 regulator-max-microvolt = <3300000>;
[all …]
H A Dat91-sama5d3_eds.dts1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
3 * at91-sama5d3_eds.dts - Device Tree file for the SAMA5D3 Ethernet
10 /dts-v1/;
15 compatible = "microchip,sama5d3-eds", "atmel,sama5d36",
19 stdout-path = "serial0:115200n8";
22 gpio-keys {
23 compatible = "gpio-keys";
25 pinctrl-names = "default";
26 pinctrl-0 = <&pinctrl_key_gpio>;
28 button-3 {
[all …]
H A Dat91sam9x5ek.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board
11 model = "Atmel AT91SAM9X5-EK";
16 stdout-path = "serial0:115200n8";
20 compatible = "atmel,sam9x5-wm8731-audio";
24 atmel,audio-routing =
30 atmel,ssc-controller = <&ssc0>;
31 atmel,audio-codec = <&wm8731>;
36 atmel,adc-ts-wires = <4>;
37 atmel,adc-ts-pressure-threshold = <10000>;
[all …]
H A Dat91sam9n12ek.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9n12ek.dts - Device Tree file for AT91SAM9N12-EK board
8 /dts-v1/;
12 model = "Atmel AT91SAM9N12-EK";
17 stdout-path = "serial0:115200n8";
26 clock-frequency = <32768>;
30 clock-frequency = <16000000>;
46 compatible = "atmel,tcb-timer";
51 compatible = "atmel,tcb-timer";
63 clock-names = "mclk";
[all …]
H A Dat91sam9m10g45ek.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board
8 /dts-v1/;
10 #include <dt-bindings/pwm/pwm.h>
13 model = "Atmel AT91SAM9M10G45-EK";
18 stdout-path = "serial0:115200n8";
27 clock-frequency = <32768>;
31 clock-frequency = <12000000>;
43 compatible = "atmel,tcb-timer";
48 compatible = "atmel,tcb-timer";
[all …]
/openbmc/linux/arch/arm/boot/dts/actions/
H A Dowl-s500-roseapplepi.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
5 * Copyright (C) 2020-2021 Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
8 /dts-v1/;
10 #include "owl-s500.dtsi"
17 mmc0 = &mmc0;
22 stdout-path = "serial2:115200n8";
30 syspwr: regulator-5v0 {
31 compatible = "regulator-fixed";
32 regulator-name = "SYSPWR";
33 regulator-min-microvolt = <5000000>;
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dat91sam9x5ek.dtsi2 * at91sam9x5ek.dtsi - Device Tree file for AT91SAM9x5CM Base board
12 model = "Atmel AT91SAM9X5-EK";
17 stdout-path = "serial0:115200n8";
18 u-boot,dm-pre-reloc;
23 mmc0: mmc@f0008000 { label
24 pinctrl-0 = <
31 bus-width = <4>;
32 cd-gpios = <&pioD 15 GPIO_ACTIVE_HIGH>;
37 pinctrl-0 = <
44 bus-width = <4>;
[all …]
H A Dat91sam9n12ek.dts2 * at91sam9n12ek.dts - Device Tree file for AT91SAM9N12-EK board
9 /dts-v1/;
13 model = "Atmel AT91SAM9N12-EK";
18 stdout-path = "serial0:115200n8";
19 u-boot,dm-pre-reloc;
28 clock-frequency = <32768>;
32 clock-frequency = <16000000>;
39 u-boot,dm-pre-reloc;
54 clock-names = "mclk";
60 interrupt-parent = <&pioA>;
[all …]
H A Dat91sam9m10g45ek.dts2 * at91sam9m10g45ek.dts - Device Tree file for AT91SAM9M10G45-EK board
9 /dts-v1/;
11 #include <dt-bindings/pwm/pwm.h>
14 model = "Atmel AT91SAM9M10G45-EK";
19 stdout-path = "serial0:115200n8";
20 u-boot,dm-pre-reloc;
29 clock-frequency = <32768>;
33 clock-frequency = <12000000>;
41 u-boot,dm-pre-reloc;
45 pinctrl-0 =
[all …]
H A Dsun50i-h6.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ or MIT)
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/clock/sun50i-h6-ccu.h>
8 #include <dt-bindings/clock/sun50i-h6-r-ccu.h>
9 #include <dt-bindings/reset/sun50i-h6-ccu.h>
10 #include <dt-bindings/reset/sun50i-h6-r-ccu.h>
13 interrupt-parent = <&gic>;
14 #address-cells = <1>;
15 #size-cells = <1>;
18 #address-cells = <1>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/mediatek/
H A Dmt7986a-rfb.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 /dts-v1/;
8 #include <dt-bindings/pinctrl/mt65xx.h>
14 chassis-type = "embedded";
15 compatible = "mediatek,mt7986a-rfb", "mediatek,mt7986a";
22 stdout-path = "serial0:115200n8";
30 reg_1p8v: regulator-1p8v {
31 compatible = "regulator-fixed";
32 regulator-name = "fixed-1.8V";
33 regulator-min-microvolt = <1800000>;
[all …]
H A Dmt6795-sony-xperia-m5.dts1 // SPDX-License-Identifier: GPL-2.0-only
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
14 compatible = "sony,xperia-m5", "mediatek,mt6795";
15 chassis-type = "handset";
18 mmc0 = &mmc0;
30 reserved_memory: reserved-memory {
31 #address-cells = <2>;
32 #size-cells = <2>;
38 no-map;
[all …]
H A Dmt8365-evk.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2021-2022 BayLibre, SAS.
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/mt8365-pinfunc.h>
19 compatible = "mediatek,mt8365-evk", "mediatek,mt8365";
26 stdout-path = "serial0:921600n8";
31 compatible = "linaro,optee-tz";
36 gpio-keys {
[all …]
H A Dmt8183-kukui.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
16 mmc0 = &mmc0;
21 stdout-path = "serial0:115200n8";
25 compatible = "pwm-backlight";
27 power-supply = <&bl_pp5000>;
28 enable-gpios = <&pio 176 0>;
29 brightness-levels = <0 1023>;
30 num-interpolated-steps = <1023>;
[all …]
H A Dmt7986a-bananapi-bpi-r3.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
5 * Frank Wunderlich <frank-w@public-files.de>
9 /dts-v1/;
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/input/input.h>
12 #include <dt-bindings/leds/common.h>
13 #include <dt-bindings/pinctrl/mt65xx.h>
18 model = "Bananapi BPI-R3";
19 chassis-type = "embedded";
20 compatible = "bananapi,bpi-r3", "mediatek,mt7986a";
[all …]
H A Dmt8195-demo.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/input/input.h>
13 #include <dt-bindings/pinctrl/mt8195-pinfunc.h>
14 #include <dt-bindings/regulator/mediatek,mt6360-regulator.h>
18 compatible = "mediatek,mt8195-demo", "mediatek,mt8195";
25 stdout-path = "serial0:921600n8";
30 compatible = "linaro,optee-tz";
35 gpio-keys {
[all …]
H A Dmt8195-cherry.dtsi1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/spmi/spmi.h>
20 mmc0 = &mmc0;
25 backlight_lcd0: backlight-lcd0 {
26 compatible = "pwm-backlight";
27 brightness-levels = <0 1023>;
28 default-brightness-level = <576>;
29 enable-gpios = <&pio 82 GPIO_ACTIVE_HIGH>;
30 num-interpolated-steps = <1023>;
[all …]
/openbmc/linux/arch/riscv/boot/dts/starfive/
H A Djh7110-starfive-visionfive-2.dtsi1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
9 #include "jh7110-pinfunc.h"
10 #include <dt-bindings/gpio/gpio.h>
20 mmc0 = &mmc0;
26 stdout-path = "serial0:115200n8";
30 timebase-frequency = <4000000>;
38 gpio-restart {
39 compatible = "gpio-restart";
46 clock-frequency = <74250000>;
[all …]
/openbmc/linux/Documentation/driver-api/
H A Dpin-control.rst9 - Enumerating and naming controllable pins
11 - Multiplexing of pins, pads, fingers (etc) see below for details
13 - Configuration of pins, pads, fingers (etc), such as software-controlled
14 biasing and driving mode specific pins, such as pull-up, pull-down, open drain,
17 Top-level interface
22 - A PIN CONTROLLER is a piece of hardware, usually a set of registers, that
23 can control PINs. It may be able to multiplex, bias, set load capacitance,
24 set drive strength, etc. for individual pins or groups of pins.
26 - PINS are equal to pads, fingers, balls or whatever packaging input or
30 be sparse - i.e. there may be gaps in the space with numbers where no
[all …]
/openbmc/linux/arch/arm/boot/dts/rockchip/
H A Drk3066a-mk808.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/input/input.h>
15 mmc0 = &mmc0;
20 stdout-path = "serial2:115200n8";
28 adc-keys {
29 compatible = "adc-keys";
30 io-channels = <&saradc 1>;
31 io-channel-names = "buttons";
32 keyup-threshold-microvolt = <2500000>;
[all …]
H A Drk3188-radxarock.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/input/input.h>
15 mmc0 = &mmc0;
23 gpio-keys {
24 compatible = "gpio-keys";
27 key-power {
31 linux,input-type = <1>;
32 wakeup-source;
33 debounce-interval = <100>;
[all …]
H A Drk3066a-rayeager.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
7 #include <dt-bindings/input/input.h>
12 compatible = "chipspark,rayeager-px2", "rockchip,rk3066a";
15 mmc0 = &mmc0;
25 ir: ir-receiver {
26 compatible = "gpio-ir-receiver";
28 pinctrl-names = "default";
29 pinctrl-0 = <&ir_int>;
32 keys: gpio-keys {
[all …]
/openbmc/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa300-raumfeld-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6 #include <dt-bindings/interrupt-controller/irq.h>
10 hw-revision = <0>;
14 stdout-path = &ffuart;
22 reg_3v3: regulator-3v3 {
23 compatible = "regulator-fixed";
24 regulator-name = "3v3-fixed-supply";
25 regulator-min-microvolt = <3300000>;
[all …]
/openbmc/linux/arch/arm/boot/dts/allwinner/
H A Dsuniv-f1c100s.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
7 #include <dt-bindings/clock/suniv-ccu-f1c100s.h>
8 #include <dt-bindings/reset/suniv-ccu-f1c100s.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
13 interrupt-parent = <&intc>;
16 osc24M: clk-24M {
17 #clock-cells = <0>;
18 compatible = "fixed-clock";
19 clock-frequency = <24000000>;
[all …]

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