Merge tag 'v6.6.52' into for/openbmc/dev-6.6

This is the 6.6.52 stable release

riscv: dts: starfive: add assigned-clock* to limit frquency

commit af571133f7ae028ec9b5fdab78f483af13bf28d3 upstream.

In JH7110 SoC, we need to go by-pass mode, so we need add the
assigned-clock* p

riscv: dts: starfive: add assigned-clock* to limit frquency

commit af571133f7ae028ec9b5fdab78f483af13bf28d3 upstream.

In JH7110 SoC, we need to go by-pass mode, so we need add the
assigned-clock* properties to limit clock frquency.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: WangYuli <wangyuli@uniontech.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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Merge tag 'v6.6.34' into dev-6.6

This is the 6.6.34 stable release

riscv: dts: starfive: Remove PMIC interrupt info for Visionfive 2 board

commit 0f74c64f0a9f6e1e7cf17bea3d4350fa6581e0d7 upstream.

Interrupt line number of the AXP15060 PMIC is not a necessary part

riscv: dts: starfive: Remove PMIC interrupt info for Visionfive 2 board

commit 0f74c64f0a9f6e1e7cf17bea3d4350fa6581e0d7 upstream.

Interrupt line number of the AXP15060 PMIC is not a necessary part of
its device tree. Originally the binding required one, so the dts patch
added an invalid interrupt that the driver ignored (0) as the interrupt
line of the PMIC is not actually connected on this platform. This went
unnoticed during review as it would have been a valid interrupt for a
GPIO controller, but it is not for the PLIC. The PLIC, on this platform
at least, silently ignores the enablement of interrupt 0. Bo Gan is
running a modified version of OpenSBI that faults if writes are done to
reserved fields, so their kernel runs into problems.

Delete the invalid interrupt from the device tree.

Cc: stable@vger.kernel.org
Reported-by: Bo Gan <ganboing@gmail.com>
Link: https://lore.kernel.org/all/c8b6e960-2459-130f-e4e4-7c9c2ebaa6d3@gmail.com/
Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
Fixes: 2378341504de ("riscv: dts: starfive: Enable axp15060 pmic for cpufreq")
[conor: rewrite the commit message to add more detail]
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

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Merge tag 'v6.6.33' into dev-6.6

This is the 6.6.33 stable release

riscv: dts: starfive: visionfive 2: Remove non-existing TDM hardware

[ Upstream commit dcde4e97b122ac318aaa71e8bcd2857dc28a0d12 ]

This partially reverts
commit e7c304c0346d ("riscv: dts: starfive:

riscv: dts: starfive: visionfive 2: Remove non-existing TDM hardware

[ Upstream commit dcde4e97b122ac318aaa71e8bcd2857dc28a0d12 ]

This partially reverts
commit e7c304c0346d ("riscv: dts: starfive: jh7110: add the node and pins configuration for tdm")

This added device tree nodes for TDM hardware that is not actually on the
VisionFive 2 board, but connected on the 40pin header. Many different extension
boards could be added on those pins, so this should be handled by overlays
instead.
This also conflicts with the I2S node which also attempts to grab GPIO 44:

starfive-jh7110-sys-pinctrl 13040000.pinctrl: pin GPIO44 already requested by 10090000.tdm; cannot claim for 120c0000.i2s

Fixes: e7c304c0346d ("riscv: dts: starfive: jh7110: add the node and pins configuration for tdm")
Signed-off-by: Hannah Peuckmann <hannah.peuckmann@canonical.com>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Tested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>

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Merge tag 'soc-fixes-6.7-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Arnd Bergmann:
"A couple of platforms have some last-minute fixes, in particular:

-

Merge tag 'soc-fixes-6.7-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Arnd Bergmann:
"A couple of platforms have some last-minute fixes, in particular:

- riscv gets some fixes for noncoherent DMA on the renesas and thead
platforms and dts fix for SPI on the visionfive 2 board

- Qualcomm Snapdragon gets three dts fixes to address board specific
regressions on the pmic and gpio nodes

- Rockchip platforms get multiple dts fixes to address issues on the
recent rk3399 platform as well as the older rk3128 platform that
apparently regressed a while ago.

- TI OMAP gets some trivial code and dts fixes and a regression fix
for the omap1 ams-delta modem

- NXP i.MX firmware has one fix for a use-after-free but in its error
handling"

* tag 'soc-fixes-6.7-3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (25 commits)
soc: renesas: ARCH_R9A07G043 depends on !RISCV_ISA_ZICBOM
riscv: only select DMA_DIRECT_REMAP from RISCV_ISA_ZICBOM and ERRATA_THEAD_PBMT
riscv: RISCV_NONSTANDARD_CACHE_OPS shouldn't depend on RISCV_DMA_NONCOHERENT
riscv: dts: thead: set dma-noncoherent to soc bus
arm64: dts: rockchip: Fix i2s0 pin conflict on ROCK Pi 4 boards
arm64: dts: rockchip: Add i2s0-2ch-bus-bclk-off pins to RK3399
clk: ti: Fix missing omap5 mcbsp functional clock and aliases
clk: ti: Fix missing omap4 mcbsp functional clock and aliases
ARM: OMAP1: ams-delta: Fix MODEM initialization failure
soc: renesas: Make ARCH_R9A07G043 depend on required options
riscv: dts: starfive: visionfive 2: correct spi's ss pin
firmware/imx-dsp: Fix use_after_free in imx_dsp_setup_channels()
ARM: OMAP: timer32K: fix all kernel-doc warnings
ARM: omap2: fix a debug printk
ARM: dts: rockchip: Fix timer clocks for RK3128
ARM: dts: rockchip: Add missing quirk for RK3128's dma engine
ARM: dts: rockchip: Add missing arm timer interrupt for RK3128
ARM: dts: rockchip: Fix i2c0 register address for RK3128
arm64: dts: rockchip: set codec system-clock-fixed on px30-ringneck-haikou
arm64: dts: rockchip: use codec as clock master on px30-ringneck-haikou
...

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Merge tag 'riscv-dt-for-v6.6-final' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into arm/fixes

RISC-V Devicetrees for v6.6-final

A single fix for the Starfive VisionFive 2 platfo

Merge tag 'riscv-dt-for-v6.6-final' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into arm/fixes

RISC-V Devicetrees for v6.6-final

A single fix for the Starfive VisionFive 2 platform so that chip select
for SPI matches the vendor documentation.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

* tag 'riscv-dt-for-v6.6-final' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
riscv: dts: starfive: visionfive 2: correct spi's ss pin

Link: https://lore.kernel.org/r/20231015-outmatch-tragedy-228f91d396b5@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

show more ...

riscv: dts: starfive: visionfive 2: correct spi's ss pin

The ss pin of spi0 is the same as sck pin. According to the
visionfive 2 documentation, it should be pin 49 instead of 48.

Fixes: 74fb20c8f0

riscv: dts: starfive: visionfive 2: correct spi's ss pin

The ss pin of spi0 is the same as sck pin. According to the
visionfive 2 documentation, it should be pin 49 instead of 48.

Fixes: 74fb20c8f05d ("riscv: dts: starfive: Add spi node and pins configuration")
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Nam Cao <namcao@linutronix.de>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

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Merge tag 'soc-fixes-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Arnd Bergmann:
"These are the latest bug fixes that have come up in the soc tree. Most
o

Merge tag 'soc-fixes-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Arnd Bergmann:
"These are the latest bug fixes that have come up in the soc tree. Most
of these are fairly minor. Most notably, the majority of changes this
time are not for dts files as usual.

- Updates to the addresses of the broadcom and aspeed entries in the
MAINTAINERS file.

- Defconfig updates to address a regression on samsung and a build
warning from an unknown Kconfig symbol

- Build fixes for the StrongARM and Uniphier platforms

- Code fixes for SCMI and FF-A firmware drivers, both of which had a
simple bug that resulted in invalid data, and a lesser fix for the
optee firmware driver

- Multiple fixes for the recently added loongson/loongarch "guts" soc
driver

- Devicetree fixes for RISC-V on the startfive platform, addressing
issues with NOR flash, usb and uart.

- Multiple fixes for NXP i.MX8/i.MX9 dts files, fixing problems with
clock, gpio, hdmi settings and the Makefile

- Bug fixes for i.MX firmware code and the OCOTP soc driver

- Multiple fixes for the TI sysc bus driver

- Minor dts updates for TI omap dts files, to address boot time
warnings and errors"

* tag 'soc-fixes-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (35 commits)
MAINTAINERS: Fix Florian Fainelli's email address
arm64: defconfig: enable syscon-poweroff driver
ARM: locomo: fix locomolcd_power declaration
soc: loongson: loongson2_guts: Remove unneeded semicolon
soc: loongson: loongson2_guts: Convert to devm_platform_ioremap_resource()
soc: loongson: loongson_pm2: Populate children syscon nodes
dt-bindings: soc: loongson,ls2k-pmc: Allow syscon-reboot/syscon-poweroff as child
soc: loongson: loongson_pm2: Drop useless of_device_id compatible
dt-bindings: soc: loongson,ls2k-pmc: Use fallbacks for ls2k-pmc compatible
soc: loongson: loongson_pm2: Add dependency for INPUT
arm64: defconfig: remove CONFIG_COMMON_CLK_NPCM8XX=y
ARM: uniphier: fix cache kernel-doc warnings
MAINTAINERS: aspeed: Update Andrew's email address
MAINTAINERS: aspeed: Update git tree URL
firmware: arm_ffa: Don't set the memory region attributes for MEM_LEND
arm64: dts: imx: Add imx8mm-prt8mm.dtb to build
arm64: dts: imx8mm-evk: Fix hdmi@3d node
soc: imx8m: Enable OCOTP clock for imx8mm before reading registers
arm64: dts: imx8mp-beacon-kit: Fix audio_pll2 clock
arm64: dts: imx8mp: Fix SDMA2/3 clocks
...

show more ...

Merge tag 'riscv-dt-fixes-for-v6.6-rc3' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into arm/fixes

RISC-V Devicetree fixes for v6.6-rc3

Starfive:
A fix for the size of the NOR fl

Merge tag 'riscv-dt-fixes-for-v6.6-rc3' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into arm/fixes

RISC-V Devicetree fixes for v6.6-rc3

Starfive:
A fix for the size of the NOR flash that was causing complaints from the
MTD subsystem during boot & two issues that a certain someone introduced
while resolving merge conflicts. Of the latter, one is a cosmetic
ordering change & the other lead to the usb controller being disabled.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

* tag 'riscv-dt-fixes-for-v6.6-rc3' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux:
riscv: dts: starfive: visionfive 2: Fix uart0 pins sort order
riscv: dts: starfive: visionfive 2: Enable usb0
riscv: dts: starfive: fix NOR flash reserved-data partition size

Link: https://lore.kernel.org/r/20230916-previous-oversold-9d30891ac6cf@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

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riscv: dts: starfive: visionfive 2: Fix uart0 pins sort order

Node uart0_pins should be sorted alphabetically.

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor

riscv: dts: starfive: visionfive 2: Fix uart0 pins sort order

Node uart0_pins should be sorted alphabetically.

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

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riscv: dts: starfive: visionfive 2: Enable usb0

usb0 was disabled by mistake when merging, so enable it.

Fixes: e7c304c0346d ("riscv: dts: starfive: jh7110: add the node and pins configuration for

riscv: dts: starfive: visionfive 2: Enable usb0

usb0 was disabled by mistake when merging, so enable it.

Fixes: e7c304c0346d ("riscv: dts: starfive: jh7110: add the node and pins configuration for tdm")
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

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riscv: dts: starfive: fix NOR flash reserved-data partition size

The Starfive VisionFive 2 has a 16MiB NOR flash, while the reserved-data
partition is declared starting at address 0x600000 with a si

riscv: dts: starfive: fix NOR flash reserved-data partition size

The Starfive VisionFive 2 has a 16MiB NOR flash, while the reserved-data
partition is declared starting at address 0x600000 with a size of
0x1000000. This causes the kernel to output the following warning:

[ 22.156589] mtd: partition "reserved-data" extends beyond the end of device "13010000.spi.0" -- size truncated to 0xa00000

It seems to be a confusion between the size of the partition and the end
address. Fix that by specifying the right size.

Fixes: 8384087a4223 ("riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC")
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

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Merge drm/drm-fixes into drm-misc-fixes

Forwarding to v6.6-rc1.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>

Merge tag 'soc-dt-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM devicetree updates from Arnd Bergmann:
"These are the devicetree updates for Arm and RISC-V based SoCs, main

Merge tag 'soc-dt-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM devicetree updates from Arnd Bergmann:
"These are the devicetree updates for Arm and RISC-V based SoCs, mainly
from Qualcomm, NXP/Freescale, Aspeed, TI, Rockchips, Samsung, ST and
Starfive.

Only a few new SoC got added:

- TI AM62P5, a variant of the existing Sitara AM62x family

- Intel Agilex5, an FPGFA platform that includes an Cortex-A76/A55
SoC.

- Qualcomm ipq5018 is used in wireless access points

- Qualcomm SM4450 (Snapdragon 4 Gen 2) is a new low-end mobile phone
platform.

In total, 29 machines get added, which is low because of the summer
break. These cover SoCs from Aspeed, Broadcom, NXP, Samsung, ST,
Allwinner, Amlogic, Intel, Qualcomm, Rockchip, TI and T-Head. Most of
these are development and reference boards.

Despite not adding a lot of new machines, there are over 700 patches
in total, most of which are cleanups and minor fixes"

* tag 'soc-dt-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (735 commits)
arm64: dts: use capital "OR" for multiple licenses in SPDX
ARM: dts: use capital "OR" for multiple licenses in SPDX
arm64: dts: qcom: sdm845-db845c: Mark cont splash memory region as reserved
ARM: dts: qcom: apq8064: add support to gsbi4 uart
riscv: dts: change TH1520 files to dual license
riscv: dts: thead: add BeagleV Ahead board device tree
dt-bindings: riscv: Add BeagleV Ahead board compatibles
ARM: dts: stm32: add SCMI PMIC regulators on stm32mp135f-dk board
ARM: dts: stm32: STM32MP13x SoC exposes SCMI regulators
dt-bindings: rcc: stm32: add STM32MP13 SCMI regulators IDs
ARM: dts: stm32: support display on stm32f746-disco board
ARM: dts: stm32: rename mmc_vcard to vcc-3v3 on stm32f746-disco
ARM: dts: stm32: add pin map for LTDC on stm32f7
ARM: dts: stm32: add ltdc support on stm32f746 MCU
arm64: dts: qcom: sm6350: Hook up PDC as wakeup-parent of TLMM
arm64: dts: qcom: sdm670: Hook up PDC as wakeup-parent of TLMM
arm64: dts: qcom: sa8775p: Hook up PDC as wakeup-parent of TLMM
arm64: dts: qcom: sc8280xp: Hook up PDC as wakeup-parent of TLMM
arm64: dts: qcom: sdm670: Add PDC
riscv: dts: starfive: fix jh7110 qspi sort order
...

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Merge branch 'next' into for-linus

Prepare input updates for 6.6 merge window.

Merge tag 'riscv-dt-for-v6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt

RISC-V Devicetrees for v6.6

StarFive:
There's only StarFive stuff this time around, starting

Merge tag 'riscv-dt-for-v6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux into soc/dt

RISC-V Devicetrees for v6.6

StarFive:
There's only StarFive stuff this time around, starting with some
bindings to get clock ID defines out of the binding headers. Getting
these (and the syscon bindings) in unblocked a swathe of stuff sitting
on the list. Added are: new clock controllers and sycons, ethernet
support, thermal sensors, USB and PCIe PHYs, hwrng, mmc and a few more
besides for the VisionFive v2. The original VisionFive and BeagleV
Starlight got some the thermal sensor support too, as that is supported
by the same driver. These changes make the board actually usable with
something other than an initramfs.
Overlay support by way of the -@ flag set during dtb building, is added
also.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

* tag 'riscv-dt-for-v6.6' of https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux: (26 commits)
riscv: dts: starfive: jh7110: Fix GMAC configuration
riscv: dts: starfive - Add hwrng node for JH7110 SoC
riscv: dts: starfive - Add crypto and DMA node for JH7110
riscv: dts: starfive: Add mmc nodes on VisionFive 2 board
riscv: dts: starfive: enable DCDC1&ALDO4 node in axp15060
riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC
riscv: dts: starfive: jh7110: add the node and pins configuration for tdm
riscv: dts: starfive: jh7110: add dma controller node
riscv: dts: starfive: Add spi node and pins configuration
riscv: dts: starfive: Add USB dts node for JH7110
riscv: dts: starfive: Add USB and PCIe PHY nodes for JH7110
riscv: dts: starfive: jh7110: Add temperature sensor node and thermal-zones
riscv: dts: starfive: jh7100: Add temperature sensor node and thermal-zones
riscv: dts: starfive: visionfive 2: Add configuration of gmac and phy
riscv: dts: starfive: jh7110: Add ethernet device nodes
riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG node
riscv: dts: starfive: jh7110: Add syscon nodes
riscv: dts: starfive: jh7110: Add STGCRG/ISPCRG/VOUTCRG nodes
riscv: dts: starfive: jh7110: Add DVP and HDMI TX pixel external clocks
dt-bindings: clock: Add StarFive JH7110 Video-Output clock and reset generator
...

Link: https://lore.kernel.org/r/20230813-naturist-fragment-ac7d10c453ba@spud
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

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riscv: dts: starfive: Add mmc nodes on VisionFive 2 board

Add the mmc nodes for the StarFive JH7110 SoC.
Set mmc0 node to emmc and set mmc1 node to sd.

Signed-off-by: William Qiu <william.qiu@starf

riscv: dts: starfive: Add mmc nodes on VisionFive 2 board

Add the mmc nodes for the StarFive JH7110 SoC.
Set mmc0 node to emmc and set mmc1 node to sd.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

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riscv: dts: starfive: enable DCDC1&ALDO4 node in axp15060

Enable DCDC1 node for vmmc-supply and enable ALDO4 node for
vqmmc-supply.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Signed-

riscv: dts: starfive: enable DCDC1&ALDO4 node in axp15060

Enable DCDC1 node for vmmc-supply and enable ALDO4 node for
vqmmc-supply.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

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Merge drm/drm-next into drm-intel-next

Catching-up with drm-next and drm-intel-gt-next.
It will unblock a code refactor around the platform
definitions (names vs acronyms).

Signed-off-by: Rodrigo V

Merge drm/drm-next into drm-intel-next

Catching-up with drm-next and drm-intel-gt-next.
It will unblock a code refactor around the platform
definitions (names vs acronyms).

Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

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Merge drm/drm-next into drm-intel-gt-next

Need to pull in b3e4aae612ec ("drm/i915/hdcp: Modify hdcp_gsc_message msg sending mechanism") as
a dependency for https://patchwork.freedesktop.org/series/1

Merge drm/drm-next into drm-intel-gt-next

Need to pull in b3e4aae612ec ("drm/i915/hdcp: Modify hdcp_gsc_message msg sending mechanism") as
a dependency for https://patchwork.freedesktop.org/series/121735/

Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

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riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC

Add the quad spi controller node for the StarFive JH7110 SoC.

Co-developed-by: Ziv Xu <ziv.xu@starfivetech.com>
Signed-off-by:

riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC

Add the quad spi controller node for the StarFive JH7110 SoC.

Co-developed-by: Ziv Xu <ziv.xu@starfivetech.com>
Signed-off-by: Ziv Xu <ziv.xu@starfivetech.com>
Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

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riscv: dts: starfive: jh7110: add the node and pins configuration for tdm

Add the tdm controller node and pins configuration of tdm for the
StarFive JH7110 SoC.

Reviewed-by: Hal Feng <hal.feng@star

riscv: dts: starfive: jh7110: add the node and pins configuration for tdm

Add the tdm controller node and pins configuration of tdm for the
StarFive JH7110 SoC.

Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Walker Chen <walker.chen@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

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riscv: dts: starfive: Add spi node and pins configuration

Add StarFive JH7110 SPI controller node and pins configuration on
VisionFive 2 board.

Signed-off-by: William Qiu <william.qiu@starfivetech.

riscv: dts: starfive: Add spi node and pins configuration

Add StarFive JH7110 SPI controller node and pins configuration on
VisionFive 2 board.

Signed-off-by: William Qiu <william.qiu@starfivetech.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

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