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/openbmc/linux/Documentation/devicetree/bindings/mmc/
H A Darasan,sdhci.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Adrian Hunter <adrian.hunter@intel.com>
13 - $ref: mmc-controller.yaml#
14 - if:
18 const: arasan,sdhci-5.1
21 - phys
22 - phy-names
23 - if:
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/openbmc/linux/arch/arm64/boot/dts/xilinx/
H A Dzynqmp-zc1751-xm015-dc1.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm015-dc1
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/phy/phy.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 model = "ZynqMP zc1751-xm015-dc1 RevA";
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H A Dzynqmp-zcu100-revC.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
12 /dts-v1/;
15 #include "zynqmp-clk-ccf.dtsi"
16 #include <dt-bindings/input/input.h>
17 #include <dt-bindings/interrupt-controller/irq.h>
18 #include <dt-bindings/gpio/gpio.h>
19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 #include <dt-bindings/phy/phy.h>
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H A Dzynqmp-sck-kv-g-revB.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 #include <dt-bindings/gpio/gpio.h>
12 #include <dt-bindings/net/ti-dp83867.h>
13 #include <dt-bindings/phy/phy.h>
14 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
16 /dts-v1/;
20 si5332_0: si5332-0 { /* u17 */
21 compatible = "fixed-clock";
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H A Dzynqmp-sck-kv-g-revA.dtso1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2020 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
9 * "A" - A01 board un-modified (NXP)
10 * "Y" - A01 board modified with legacy interposer (Nexperia)
11 * "Z" - A01 board modified with Diode interposer
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/net/ti-dp83867.h>
18 #include <dt-bindings/phy/phy.h>
19 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
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H A Dzynqmp-sm-k26-revA.dts1 // SPDX-License-Identifier: GPL-2.0
3 * dts file for Xilinx ZynqMP SM-K26 rev1/B/A
5 * (C) Copyright 2020 - 2021, Xilinx, Inc.
10 /dts-v1/;
13 #include "zynqmp-clk-ccf.dtsi"
14 #include <dt-bindings/input/input.h>
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/phy/phy.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
20 model = "ZynqMP SM-K26 Rev1/B/A";
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H A Dzynqmp-zc1751-xm019-dc5.dts1 // SPDX-License-Identifier: GPL-2.0+
3 * dts file for Xilinx ZynqMP zc1751-xm019-dc5
5 * (C) Copyright 2015 - 2021, Xilinx, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
19 model = "ZynqMP zc1751-xm019-dc5 RevA";
20 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
33 stdout-path = "serial0:115200n8";
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H A Dzynqmp-zcu104-revC.dts1 // SPDX-License-Identifier: GPL-2.0
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
21 compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
38 stdout-path = "serial0:115200n8";
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H A Dzynqmp-zcu104-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/gpio/gpio.h>
16 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
17 #include <dt-bindings/phy/phy.h>
21 compatible = "xlnx,zynqmp-zcu104-revA", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
38 stdout-path = "serial0:115200n8";
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H A Dzynqmp-zcu111-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2017 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
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H A Dzynqmp-zcu106-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2016 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu106-revA", "xlnx,zynqmp-zcu106", "xlnx,zynqmp";
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H A Dzynqmp-zcu102-revA.dts1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2015 - 2022, Xilinx, Inc.
6 * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc.
11 /dts-v1/;
14 #include "zynqmp-clk-ccf.dtsi"
15 #include <dt-bindings/input/input.h>
16 #include <dt-bindings/gpio/gpio.h>
17 #include <dt-bindings/pinctrl/pinctrl-zynqmp.h>
18 #include <dt-bindings/phy/phy.h>
22 compatible = "xlnx,zynqmp-zcu102-revA", "xlnx,zynqmp-zcu102", "xlnx,zynqmp";
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/openbmc/linux/drivers/comedi/drivers/
H A Dpcmmio.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Driver for Winsystems PC-104 based multifunction IO board.
6 * COMEDI - Linux Control and Measurement Device Interface
12 * Description: A driver for the PCM-MIO multifunction board
13 * Devices: [Winsystems] PCM-MIO (pcmmio)
15 * Updated: Wed, May 16 2007 16:21:10 -0500
18 * A driver for the PCM-MIO multifunction board from Winsystems. This
19 * is a PC-104 based I/O board. It contains four subdevices:
21 * subdevice 0 - 16 channels of 16-bit AI
22 * subdevice 1 - 8 channels of 16-bit AO
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/openbmc/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra30.c1 // SPDX-License-Identifier: GPL-2.0-only
7 * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved.
16 #include "pinctrl-tegra.h"
273 /* All non-GPIO pins follow */
277 /* Non-GPIO pins */
2050 FUNCTION(mio),
2099 #define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
2100 #define PINGROUP_REG_A 0x3000 /* bank 1 */
2102 #define DRV_PINGROUP_REG(r) ((r) - DRV_PINGROUP_REG_A)
2103 #define PINGROUP_REG(r) ((r) - PINGROUP_REG_A)
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/openbmc/linux/arch/mips/include/asm/sn/
H A Dklconfig.h8 * Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc.
85 /* lboard_t->brd_flags fields */
97 #define SECOND_NIC_PRESENT 0x80 /* addons like MIO are present */
99 /* klinfo->flags fields */
108 #define IS_CONSOLE_IOC3(i) ((((klinfo_t *)i)->flags) & KLINFO_INSTALL)
162 (KL_CONFIG_HDR(_nasid)->ch_board_info)
164 (KL_CONFIG_HDR(_nasid)->ch_board_info = (_off))
167 (lboard_t *)((KL_CONFIG_HDR(_nasid)->ch_board_info) ? \
168 NODE_OFFSET_TO_K1((_nasid), KL_CONFIG_HDR(_nasid)->ch_board_info) : \
170 #define KL_CONFIG_MAGIC(_nasid) (KL_CONFIG_HDR(_nasid)->ch_magic)
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/openbmc/u-boot/board/xilinx/zynq/zynq-zc702/
H A Dps7_init_gpl.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
2051 // .. START: MIO PROGRAMMING
3602 // .. FINISH: MIO PROGRAMMING
3762 // .. .. .. .. START: DIR MODE BANK 0
3768 // .. .. .. .. FINISH: DIR MODE BANK 0
3769 // .. .. .. .. START: DIR MODE BANK 1
3770 // .. .. .. .. FINISH: DIR MODE BANK 1
3771 // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
3780 // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
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/openbmc/u-boot/board/xilinx/zynq/zynq-zc706/
H A Dps7_init_gpl.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
2020 // .. START: MIO PROGRAMMING
3571 // .. FINISH: MIO PROGRAMMING
3731 // .. .. .. .. START: DIR MODE BANK 0
3737 // .. .. .. .. FINISH: DIR MODE BANK 0
3738 // .. .. .. .. START: DIR MODE BANK 1
3739 // .. .. .. .. FINISH: DIR MODE BANK 1
3740 // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
3749 // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
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/openbmc/u-boot/board/xilinx/zynq/zynq-microzed/
H A Dps7_init_gpl.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
2012 // .. START: MIO PROGRAMMING
3563 // .. FINISH: MIO PROGRAMMING
3723 // .. .. .. .. START: DIR MODE BANK 0
3729 // .. .. .. .. FINISH: DIR MODE BANK 0
3730 // .. .. .. .. START: DIR MODE BANK 1
3731 // .. .. .. .. FINISH: DIR MODE BANK 1
3732 // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
3741 // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
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/openbmc/u-boot/board/xilinx/zynq/zynq-zed/
H A Dps7_init_gpl.c1 // SPDX-License-Identifier: GPL-2.0+
3 * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved.
2012 // .. START: MIO PROGRAMMING
3563 // .. FINISH: MIO PROGRAMMING
3723 // .. .. .. .. START: DIR MODE BANK 0
3724 // .. .. .. .. FINISH: DIR MODE BANK 0
3725 // .. .. .. .. START: DIR MODE BANK 1
3726 // .. .. .. .. FINISH: DIR MODE BANK 1
3727 // .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0]
3728 // .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0]
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/openbmc/u-boot/board/xilinx/zynq/zynq-zybo/
H A Dps7_init_gpl.c1 // SPDX-License-Identifier: GPL-2.0+
2020 /* .. START: MIO PROGRAMMING */
3583 /* .. FINISH: MIO PROGRAMMING */
3743 /* .. .. .. .. START: DIR MODE BANK 0 */
3744 /* .. .. .. .. FINISH: DIR MODE BANK 0 */
3745 /* .. .. .. .. START: DIR MODE BANK 1 */
3751 /* .. .. .. .. FINISH: DIR MODE BANK 1 */
3752 /* .. .. .. .. START: MASK_DATA_0_LSW HIGH BANK [15:0] */
3753 /* .. .. .. .. FINISH: MASK_DATA_0_LSW HIGH BANK [15:0] */
3754 /* .. .. .. .. START: MASK_DATA_0_MSW HIGH BANK [31:16] */
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/openbmc/linux/drivers/mmc/host/
H A Dsdhci-of-arasan.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
26 #include <linux/firmware/xlnx-zynqmp.h>
29 #include "sdhci-cqhci.h"
30 #include "sdhci-pltfm.h"
92 * On some SoCs the syscon area has a feature where the upper 16-bits of
93 * each 32-bit register act as a write mask for the lower 16-bits. This allows
101 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
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/openbmc/linux/drivers/scsi/
H A Dadvansys.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
5 * Copyright (c) 1995-2000 Advanced System Products, Inc.
6 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
34 #include <linux/dma-mapping.h>
109 #define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
125 * Narrow boards only support 12-byte commands, while wide boards
126 * extend to 16-byte commands.
391 #define ASC_IERR_BIST_PRE_TEST 0x0800 /* BIST pre-test error */
412 * is Ultra-capable or not. These tables let us convert from one to the other.
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/openbmc/linux/
H A Dopengrok1.0.log1 2024-12-28 20:07:11.902-0600 FINER t583 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c'
2 2024-12-28 20:07:11.913-0600 FINEST t583 Statistics.logIt: Added: '/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' (CAnalyzer) (took 116 ms)
3 2024-12-28 20:07:11.899-0600 FINER t593 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/tools/testing/selftests/powerpc/tm/tm-signa
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