/openbmc/linux/Documentation/devicetree/bindings/i2c/ |
H A D | opencores,i2c-ocores.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/i2c/opencores,i2c-ocores.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Peter Korsgaard <peter@korsgaard.com> 11 - Andrew Lunn <andrew@lunn.ch> 14 - $ref: /schemas/i2c/i2c-controller.yaml# 19 - items: 20 - enum: 21 - sifive,fu740-c000-i2c # Opencore based IP block FU740-C000 SoC [all …]
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H A D | microchip,corei2c.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Daire McNamara <daire.mcnamara@microchip.com> 13 - $ref: /schemas/i2c/i2c-controller.yaml# 18 - items: 19 - const: microchip,mpfs-i2c # Microchip PolarFire SoC compatible SoCs 20 - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core 21 - const: microchip,corei2c-rtl-v7 # Microchip Fabric based i2c IP core 32 clock-frequency: [all …]
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H A D | i2c-demux-pinctrl.txt | 1 Pinctrl-based I2C Bus DeMux 5 the pinctrl device tree bindings. This may be used to select one I2C IP core at 7 IP core on the SoC. The most simple example is to fall back to GPIO bitbanging 8 if your current runtime configuration hits an errata of the internal IP core. 10 +-------------------------------+ 12 | | +-----+ +-----+ 13 | +------------+ | | dev | | dev | 14 | |I2C IP Core1|--\ | +-----+ +-----+ 15 | +------------+ \-------+ | | | 16 | |Pinctrl|--|------+--------+ [all …]
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/openbmc/linux/Documentation/devicetree/bindings/media/ |
H A D | nxp,imx-mipi-csi2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/media/nxp,imx-mipi-csi2.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver 10 - Rui Miguel Silva <rmfrfs@gmail.com> 11 - Laurent Pinchart <laurent.pinchart@ideasonboard.com> 13 description: |- 14 The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2 15 receiver IP core named CSIS. The IP core originates from Samsung, and may be [all …]
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H A D | samsung,exynos4210-fimc.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/media/samsung,exynos4210-fimc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 11 - Sylwester Nawrocki <s.nawrocki@samsung.com> 15 fimc<n>, where <n> is an integer specifying the IP block instance. 20 - samsung,exynos4210-fimc 21 - samsung,exynos4212-fimc 22 - samsung,s5pv210-fimc [all …]
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/openbmc/linux/Documentation/devicetree/bindings/ |
H A D | xilinx.txt | 1 d) Xilinx IP cores 3 The Xilinx EDK toolchain ships with a set of IP cores (devices) for use 10 Each IP-core has a set of parameters which the FPGA designer can use to 14 device drivers how the IP cores are configured, but it requires the kernel 20 properties of the device node. In general, device nodes for IP-cores 23 (name): (generic-name)@(base-address) { 24 compatible = "xlnx,(ip-core-name)-(HW_VER)" 27 interrupt-parent = <&interrupt-controller-phandle>; 29 xlnx,(parameter1) = "(string-value)"; 30 xlnx,(parameter2) = <(int-value)>; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/clock/ti/ |
H A D | dra7-atl.txt | 1 Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC. 3 The ATL IP is used to generate clock to be used to synchronize baseband and 4 audio codec. A single ATL IP provides four ATL clock instances sharing the same 5 functional clock but can be configured to provide different clocks. 6 ATL can maintain a clock averages to some desired frequency based on the bws/aws 7 signals - can compensate the drift between the two ws signal. 12 Clock tree binding: 13 This binding uses the common clock binding[1]. 14 To be able to integrate the ATL clocks with DT clock tree. 16 Since the clock instances are part of a single IP this binding is used as a node [all …]
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/openbmc/linux/tools/perf/pmu-events/arch/x86/sierraforest/ |
H A D | pipeline.json | 7 …"Counts the total number of instructions in which the instruction pointer (IP) of the processor is… 15 …-speculative execution path is known. The branch prediction unit (BPU) predicts the target address… 19 "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", 25 …"BriefDescription": "Counts the number of unhalted core clock cycles [This event is alias to CPU_C… 31 "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles", 37 … "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.", 40 …T instruction. This event is not affected by core frequency changes and increments at a fixed freq… 45 "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", 51 …"BriefDescription": "Counts the number of unhalted core clock cycles [This event is alias to CPU_C…
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/openbmc/linux/tools/perf/pmu-events/arch/x86/grandridge/ |
H A D | pipeline.json | 7 …"Counts the total number of instructions in which the instruction pointer (IP) of the processor is… 15 …-speculative execution path is known. The branch prediction unit (BPU) predicts the target address… 19 "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", 25 …"BriefDescription": "Counts the number of unhalted core clock cycles [This event is alias to CPU_C… 31 "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles", 37 … "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.", 40 …T instruction. This event is not affected by core frequency changes and increments at a fixed freq… 45 "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles", 51 …"BriefDescription": "Counts the number of unhalted core clock cycles [This event is alias to CPU_C…
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/openbmc/linux/Documentation/devicetree/bindings/net/can/ |
H A D | mpc5xxx-mscan.txt | 2 ------------------------ 4 (c) 2006-2009 Secret Lab Technologies Ltd 7 fsl,mpc5200-mscan nodes 8 ----------------------- 9 In addition to the required compatible-, reg- and interrupt-properties, you can 10 also specify which clock source shall be used for the controller: 12 - fsl,mscan-clock-source : a string describing the clock source. Valid values 13 are: "ip" for ip bus clock 14 "ref" for reference clock (XTAL) 18 fsl,mpc5121-mscan nodes [all …]
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H A D | grcan.txt | 3 The GRCAN and CRHCAN CAN controllers are available in the GRLIB VHDL IP core 12 - name : Should be "GAISLER_GRCAN", "01_03d", "GAISLER_GRHCAN" or "01_034" 14 - reg : Address and length of the register set for the device 16 - freq : Frequency of the external oscillator clock in Hz (the frequency of 19 - interrupts : Interrupt number for this device 23 - systemid : If not present or if the value of the least significant 16 bits 24 of this 32-bit property is smaller than GRCAN_TXBUG_SAFE_GRLIB_VERSION 27 For further information look in the documentation for the GLIB IP core library:
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/openbmc/u-boot/doc/device-tree-bindings/clock/ |
H A D | st,stm32mp1.txt | 1 STMicroelectronics STM32MP1 clock tree initialization 4 The STM32MP clock tree initialization is based on device tree information 5 for RCC IP and on fixed clocks. 7 ------------------------------- 8 RCC CLOCK = st,stm32mp1-rcc-clk 9 ------------------------------- 11 The RCC IP is both a reset and a clock controller but this documentation only 12 describes the fields added for clock tree initialization which are not present 15 Please refer to ../mfd/st,stm32-rcc.txt for all the other properties common 20 - compatible: Should be "st,stm32mp1-rcc-clk" [all …]
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H A D | st,stm32h7-rcc.txt | 1 STMicroelectronics STM32H7 Reset and Clock Controller 4 The RCC IP is both a reset and a clock controller. 6 Please refer to clock-bindings.txt for common clock controller binding usage. 10 - compatible: Should be: 11 "st,stm32h743-rcc" 13 - reg: should be register base and length as documented in the 16 - #reset-cells: 1, see below 18 - #clock-cells : from common clock binding; shall be set to 1 20 - clocks: External oscillator clock phandle 21 - high speed external clock signal (HSE) [all …]
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/openbmc/linux/drivers/pwm/ |
H A D | pwm-tegra.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * drivers/pwm/pwm-tegra.c 5 * Tegra pulse-width-modulation controller driver 7 * Copyright (c) 2010-2020, NVIDIA Corporation. 8 * Based on arch/arm/plat-mxc/pwm.c by Sascha Hauer <s.hauer@pengutronix.de> 11 * 1. 13-bit: Frequency division (SCALE) 12 * 2. 8-bit : Pulse division (DUTY) 13 * 3. 1-bit : Enable bit 15 * The PWM clock frequency is divided by 256 before subdividing it based 16 * on the programmable frequency division value to generate the required [all …]
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/openbmc/linux/arch/arc/boot/dts/ |
H A D | hsdk.dts | 1 // SPDX-License-Identifier: GPL-2.0-only 9 /dts-v1/; 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/reset/snps,hsdk-reset.h> 18 #address-cells = <2>; 19 #size-cells = <2>; 22 … "earlycon=uart8250,mmio32,0xf0005000,115200n8 console=ttyS0,115200n8 debug print-fatal-signals=1"; 30 #address-cells = <1>; 31 #size-cells = <0>; 62 input_clk: input-clk { [all …]
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/openbmc/linux/Documentation/devicetree/bindings/clock/ |
H A D | st,stm32-rcc.txt | 1 STMicroelectronics STM32 Reset and Clock Controller 4 The RCC IP is both a reset and a clock controller. 6 Please refer to clock-bindings.txt for common clock controller binding usage. 10 - compatible: Should be: 11 "st,stm32f42xx-rcc" 12 "st,stm32f469-rcc" 13 "st,stm32f746-rcc" 14 "st,stm32f769-rcc" 16 - reg: should be register base and length as documented in the 18 - #reset-cells: 1, see below [all …]
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H A D | qoriq-clock.txt | 1 * Clock Block on Freescale QorIQ Platforms 4 SYSCLK signal. The SYSCLK input (frequency) is multiplied using 7 cores and peripheral IP blocks. 14 --------------- ------------- 18 1. Clock Block Binding 21 - compatible: Should contain a chip-specific clock block compatible 22 string and (if applicable) may contain a chassis-version clock 25 Chip-specific strings are of the form "fsl,<chip>-clockgen", such as: 26 * "fsl,p2041-clockgen" 27 * "fsl,p3041-clockgen" [all …]
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/openbmc/linux/Documentation/devicetree/bindings/display/bridge/ |
H A D | samsung,mipi-dsim.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/display/bridge/samsung,mipi-dsim.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Inki Dae <inki.dae@samsung.com> 11 - Jagan Teki <jagan@amarulasolutions.com> 12 - Marek Szyprowski <m.szyprowski@samsung.com> 21 - enum: 22 - samsung,exynos3250-mipi-dsi 23 - samsung,exynos4210-mipi-dsi [all …]
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/openbmc/linux/arch/arm64/boot/dts/renesas/ |
H A D | r8a779f0-spider-cpu.dtsi | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 8 #include <dt-bindings/gpio/gpio.h> 9 #include <dt-bindings/leds/common.h> 15 compatible = "renesas,spider-cpu", "renesas,r8a779f0"; 23 bootargs = "ignore_loglevel rw root=/dev/nfs ip=on"; 24 stdout-path = "serial0:1843200n8"; 28 compatible = "gpio-leds"; 30 led-7 { 34 function-enumerator = <7>; 37 led-8 { [all …]
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/openbmc/linux/Documentation/devicetree/bindings/ptp/ |
H A D | ptp-qoriq.txt | 1 * Freescale QorIQ 1588 timer based PTP clock 5 - compatible Should be "fsl,etsec-ptp" for eTSEC 6 Should be "fsl,fman-ptp-timer" for DPAA FMan 7 Should be "fsl,dpaa2-ptp" for DPAA2 8 Should be "fsl,enetc-ptp" for ENETC 9 - reg Offset and length of the register set for the device 10 - interrupts There should be at least two interrupts. Some devices 13 Clock Properties: 15 - fsl,cksel Timer reference clock source. 16 - fsl,tclk-period Timer reference clock period in nanoseconds. [all …]
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/openbmc/linux/arch/arm/boot/dts/microchip/ |
H A D | animeo_ip.dts | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * animeo_ip.dts - Device Tree file for Somfy Animeo IP Boards 5 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> 8 /dts-v1/; 12 model = "Somfy Animeo IP"; 13 compatible = "somfy,animeo-ip", "atmel,at91sam9260", "atmel,at91sam9"; 26 stdout-path = &usart2; 35 clock-frequency = <32768>; 39 clock-frequency = <18432000>; 47 compatible = "atmel,tcb-timer"; [all …]
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/openbmc/linux/Documentation/devicetree/bindings/spi/ |
H A D | rockchip-sfc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/spi/rockchip-sfc.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Heiko Stuebner <heiko@sntech.de> 11 - Chris Morgan <macromorgan@hotmail.com> 14 - $ref: spi-controller.yaml# 20 The rockchip sfc controller is a standalone IP with version register, 21 and the driver can handle all the feature difference inside the IP 32 - description: Bus Clock [all …]
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/openbmc/linux/include/linux/clk/ |
H A D | ti.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 3 * TI clock drivers support 10 #include <linux/clk-provider.h> 14 * struct clk_omap_reg - OMAP register declaration 15 * @offset: offset from the master IP module base address 16 * @index: index of the master IP module 26 * struct dpll_data - DPLL registers and integration data 30 * @clk_bypass: struct clk_hw pointer to the clock's bypass clock input 31 * @clk_ref: struct clk_hw pointer to the clock's reference clock input 40 * @max_multiplier: maximum valid non-bypass multiplier value (actual) [all …]
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/openbmc/linux/Documentation/devicetree/bindings/timer/ |
H A D | sifive,clint.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Palmer Dabbelt <palmer@dabbelt.com> 11 - Anup Patel <anup.patel@wdc.com> 14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive 15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor 16 interrupts. It directly connects to the timer and inter-processor interrupt 17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local 19 The clock frequency of CLINT is specified via "timebase-frequency" DT [all …]
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/openbmc/u-boot/doc/device-tree-bindings/timer/ |
H A D | atcpit100_timer.txt | 2 ------------------------------------------------------------------ 3 ATCPIT100 is a generic IP block from Andes Technology, embedded in 6 This timer is a set of compact multi-function timers, which can be 10 multi-function timer and provide the following usage scenarios: 11 One 32-bit timer 12 Two 16-bit timers 13 Four 8-bit timers 14 One 16-bit PWM 15 One 16-bit timer and one 8-bit PWM 16 Two 8-bit timer and one 8-bit PWM [all …]
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