1*410d129eSRick ChenAndestech ATCPIT100 timer 2*410d129eSRick Chen------------------------------------------------------------------ 3*410d129eSRick ChenATCPIT100 is a generic IP block from Andes Technology, embedded in 4*410d129eSRick ChenAndestech AE3XX, AE250 platforms and other designs. 5*410d129eSRick Chen 6*410d129eSRick ChenThis timer is a set of compact multi-function timers, which can be 7*410d129eSRick Chenused as pulse width modulators (PWM) as well as simple timers. 8*410d129eSRick Chen 9*410d129eSRick ChenIt supports up to 4 PIT channels. Each PIT channel is a 10*410d129eSRick Chenmulti-function timer and provide the following usage scenarios: 11*410d129eSRick ChenOne 32-bit timer 12*410d129eSRick ChenTwo 16-bit timers 13*410d129eSRick ChenFour 8-bit timers 14*410d129eSRick ChenOne 16-bit PWM 15*410d129eSRick ChenOne 16-bit timer and one 8-bit PWM 16*410d129eSRick ChenTwo 8-bit timer and one 8-bit PWM 17*410d129eSRick Chen 18*410d129eSRick ChenRequired properties: 19*410d129eSRick Chen- compatible : Should be "andestech,atcpit100" 20*410d129eSRick Chen- reg : Address and length of the register set 21*410d129eSRick Chen- interrupts : Reference to the timer interrupt 22*410d129eSRick Chen- clock-frequency : The rate in HZ in input of the Andestech ATCPIT100 timer 23*410d129eSRick Chen 24*410d129eSRick ChenExamples: 25*410d129eSRick Chen 26*410d129eSRick Chentimer0: timer@f0400000 { 27*410d129eSRick Chen compatible = "andestech,atcpit100"; 28*410d129eSRick Chen reg = <0xf0400000 0x1000>; 29*410d129eSRick Chen interrupts = <2 4>; 30*410d129eSRick Chen clock-frequency = <30000000>; 31*410d129eSRick Chen}: 32