1*d524dac9SGrant LikelyCAN Device Tree Bindings 2*d524dac9SGrant Likely------------------------ 3*d524dac9SGrant Likely 4*d524dac9SGrant Likely(c) 2006-2009 Secret Lab Technologies Ltd 5*d524dac9SGrant LikelyGrant Likely <grant.likely@secretlab.ca> 6*d524dac9SGrant Likely 7*d524dac9SGrant Likelyfsl,mpc5200-mscan nodes 8*d524dac9SGrant Likely----------------------- 9*d524dac9SGrant LikelyIn addition to the required compatible-, reg- and interrupt-properties, you can 10*d524dac9SGrant Likelyalso specify which clock source shall be used for the controller: 11*d524dac9SGrant Likely 12*d524dac9SGrant Likely- fsl,mscan-clock-source : a string describing the clock source. Valid values 13*d524dac9SGrant Likely are: "ip" for ip bus clock 14*d524dac9SGrant Likely "ref" for reference clock (XTAL) 15*d524dac9SGrant Likely "ref" is default in case this property is not 16*d524dac9SGrant Likely present. 17*d524dac9SGrant Likely 18*d524dac9SGrant Likelyfsl,mpc5121-mscan nodes 19*d524dac9SGrant Likely----------------------- 20*d524dac9SGrant LikelyIn addition to the required compatible-, reg- and interrupt-properties, you can 21*d524dac9SGrant Likelyalso specify which clock source and divider shall be used for the controller: 22*d524dac9SGrant Likely 23*d524dac9SGrant Likely- fsl,mscan-clock-source : a string describing the clock source. Valid values 24*d524dac9SGrant Likely are: "ip" for ip bus clock 25*d524dac9SGrant Likely "ref" for reference clock 26*d524dac9SGrant Likely "sys" for system clock 27*d524dac9SGrant Likely If this property is not present, an optimal CAN 28*d524dac9SGrant Likely clock source and frequency based on the system 29*d524dac9SGrant Likely clock will be selected. If this is not possible, 30*d524dac9SGrant Likely the reference clock will be used. 31*d524dac9SGrant Likely 32*d524dac9SGrant Likely- fsl,mscan-clock-divider: for the reference and system clock, an additional 33*d524dac9SGrant Likely clock divider can be specified. By default, a 34*d524dac9SGrant Likely value of 1 is used. 35*d524dac9SGrant Likely 36*d524dac9SGrant LikelyNote that the MPC5121 Rev. 1 processor is not supported. 37*d524dac9SGrant Likely 38*d524dac9SGrant LikelyExamples: 39*d524dac9SGrant Likely can@1300 { 40*d524dac9SGrant Likely compatible = "fsl,mpc5121-mscan"; 41*d524dac9SGrant Likely interrupts = <12 0x8>; 42*d524dac9SGrant Likely interrupt-parent = <&ipic>; 43*d524dac9SGrant Likely reg = <0x1300 0x80>; 44*d524dac9SGrant Likely }; 45*d524dac9SGrant Likely 46*d524dac9SGrant Likely can@1380 { 47*d524dac9SGrant Likely compatible = "fsl,mpc5121-mscan"; 48*d524dac9SGrant Likely interrupts = <13 0x8>; 49*d524dac9SGrant Likely interrupt-parent = <&ipic>; 50*d524dac9SGrant Likely reg = <0x1380 0x80>; 51*d524dac9SGrant Likely fsl,mscan-clock-source = "ref"; 52*d524dac9SGrant Likely fsl,mscan-clock-divider = <3>; 53*d524dac9SGrant Likely }; 54