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/openbmc/linux/Documentation/devicetree/bindings/reserved-memory/
H A Dreserved-memory.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reserved-memory/reserved-memory.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: /reserved-memory Child Node Common
10 - devicetree-spec@vger.kernel.org
13 Reserved memory is specified as a node under the /reserved-memory node. The
19 Each child of the reserved-memory node specifies one or more regions
25 Following the generic-names recommended practice, node names should
26 reflect the purpose of the node (ie. "framebuffer" or "dma-pool").
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/openbmc/linux/Documentation/devicetree/bindings/iommu/
H A Drockchip,iommu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/iommu/rockchip,iommu.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Rockchip IOMMU
10 - Heiko Stuebner <heiko@sntech.de>
13 A Rockchip DRM iommu translates io virtual addresses to physical addresses for
17 For information on assigning IOMMU controller to its peripheral devices,
18 see generic IOMMU bindings.
23 - rockchip,iommu
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H A Diommu.txt5 IOMMU device node:
8 An IOMMU can provide the following services:
13 Example: 32-bit DMA to 64-bit physical addresses
15 * Implement scatter-gather at page level granularity so that the device does
19 through the IOMMU and faulting when encountering accesses to unmapped
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
30 typically have a fixed association to the master device, whereas multiple-
31 master IOMMU devices can translate accesses from more than one master.
33 The device tree node of the IOMMU device's parent bus must contain a valid
34 "dma-ranges" property that describes how the physical address space of the
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/openbmc/linux/Documentation/arch/x86/
H A Dsva.rst1 .. SPDX-License-Identifier: GPL-2.0
11 same virtual addresses avoiding the need for software to translate virtual
12 addresses to physical addresses. SVA is what PCIe calls Shared Virtual
15 In addition to the convenience of using application virtual addresses
19 application page-faults. For more information please refer to the PCIe
22 Use of SVA requires IOMMU support in the platform. IOMMU is also
24 to cache translations for virtual addresses. The IOMMU driver uses the
34 Unlike Single Root I/O Virtualization (SR-IOV), Scalable IOV (SIOV) permits
40 ID (PASID), which is a 20-bit number defined by the PCIe SIG.
43 IOMMU to track I/O on a per-PASID granularity in addition to using the PCIe
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H A Diommu.rst2 x86 IOMMU Support
7 - Intel: http://www.intel.com/content/dam/www/public/us/en/documents/product-specifications/vt-dire…
8 - AMD: https://www.amd.com/system/files/TechDocs/48882_IOMMU.pdf
13 -----------
16 device scope relationships between devices and which IOMMU controls
21 - DMAR - Intel DMA Remapping table
22 - DRHD - Intel DMA Remapping Hardware Unit Definition
23 - RMRR - Intel Reserved Memory Region Reporting Structure
24 - IVRS - AMD I/O Virtualization Reporting Structure
25 - IVDB - AMD I/O Virtualization Definition Block
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/openbmc/linux/Documentation/arch/s390/
H A Dvfio-ccw.rst2 vfio-ccw: the basic infrastructure
6 ------------
9 Linux/s390. Motivation for vfio-ccw is to passthrough subchannels to a
16 - Channel programs run asynchronously on a separate (co)processor.
17 - The channel subsystem will access any memory designated by the caller
18 in the channel program directly, i.e. there is no iommu involved.
22 added to an iommu group, so as to make itself able to be managed by the
31 - A good start to know Channel I/O in general:
33 - s390 architecture:
34 s390 Principles of Operation manual (IBM Form. No. SA22-7832)
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/openbmc/linux/drivers/iommu/intel/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 # Intel IOMMU support
13 bool "Support for Intel IOMMU using DMA Remapping Devices"
34 bool "Export Intel IOMMU internals in Debugfs"
43 Expose Intel IOMMU internals in Debugfs.
45 This option is -NOT- intended for production environments, and should
46 only be enabled for debugging Intel IOMMU.
49 bool "Support for Shared Virtual Memory with Intel IOMMU"
72 option permits the IOMMU driver to set a unity map for
73 all the OS-visible memory. Hence the driver can continue
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/openbmc/linux/include/linux/
H A Diommu.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2007-2008 Advanced Micro Devices, Inc.
16 #include <uapi/linux/iommu.h>
30 * if the IOMMU page table format is equivalent.
45 /* iommu fault flags */
61 #define __IOMMU_DOMAIN_DMA_API (1U << 1) /* Domain for use in DMA-API
64 #define __IOMMU_DOMAIN_DMA_FQ (1U << 3) /* DMA-API uses flush queue */
70 * This are the possible domain-types
72 * IOMMU_DOMAIN_BLOCKED - All DMA is blocked, can be used to isolate
74 * IOMMU_DOMAIN_IDENTITY - DMA addresses are system physical addresses
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H A Dremoteproc.h47 * struct resource_table - firmware resource table header
81 * struct fw_rsc_hdr - firmware resource entry header
95 * enum fw_resource_type - types of resource entries
99 * @RSC_DEVMEM: request to iommu_map a memory-based peripheral.
126 #define FW_RSC_ADDR_ANY (-1)
129 * struct fw_rsc_carveout - physically contiguous memory request
133 * @flags: iommu protection flags
135 * @name: human-readable name of the requested memory region
146 * needed to map it (in case @rproc is using an IOMMU). Reducing the TLB
149 * If the firmware is compiled with static addresses, then @da should specify
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/openbmc/linux/drivers/gpu/drm/msm/
H A Dmsm_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/adreno-smmu-priv.h>
8 #include <linux/io-pgtable.h>
35 /* based on iommu_pgsize() in iommu.c: */
46 pgsizes = pagetable->pgsize_bitmap & GENMASK(__fls(size), 0); in calc_pgsize()
62 pgsizes = pagetable->pgsize_bitmap & ~GENMASK(pgsize_idx, 0); in calc_pgsize()
71 * and physical addresses are similarly offset within the larger page. in calc_pgsize()
73 if ((iova ^ paddr) & (pgsize_next - 1)) in calc_pgsize()
77 offset = pgsize_next - (addr_merge & (pgsize_next - 1)); in calc_pgsize()
95 struct io_pgtable_ops *ops = pagetable->pgtbl_ops; in msm_iommu_pagetable_unmap()
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/openbmc/qemu/hw/sparc/
H A Dsun4m_iommu.c2 * QEMU Sun4m iommu emulation
4 * Copyright (c) 2003-2005 Fabrice Bellard
27 #include "hw/qdev-properties.h"
32 #include "exec/address-spaces.h"
39 * "Sun-4M System Architecture (revision 2.0) by Chuck Narad", 950-1373-01,
47 #define IOMMU_RNGE_16MB 0x00000000 /* 0xff000000 -> 0xffffffff */
48 #define IOMMU_RNGE_32MB 0x00000004 /* 0xfe000000 -> 0xffffffff */
49 #define IOMMU_RNGE_64MB 0x00000008 /* 0xfc000000 -> 0xffffffff */
50 #define IOMMU_RNGE_128MB 0x0000000c /* 0xf8000000 -> 0xffffffff */
51 #define IOMMU_RNGE_256MB 0x00000010 /* 0xf0000000 -> 0xffffffff */
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/openbmc/qemu/include/sysemu/
H A Ddma.h14 #include "exec/address-spaces.h"
24 * When an IOMMU is present, bus addresses become distinct from
25 * CPU/memory physical addresses and may be a different size. Because
27 * or less have to treat these as 64-bit always to cover all (or at
69 /* Checks that the given range of addresses is valid for DMA. This is
115 * IOMMU fault).
138 * IOMMU fault). Called within RCU critical section.
159 * IOMMU fault).
180 * IOMMU fault).
197 * Use only for reads OR writes - not for read-modify-write operations.
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/openbmc/linux/arch/sparc/include/asm/
H A Diommu_32.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* iommu.h: Definitions for the sun4m IOMMU.
12 /* The iommu handles all virtual to physical address translations
15 * translated by the on chip SRMMU. The iommu and the srmmu do
18 * Basically the iommu handles all dvma sbus activity.
21 /* The IOMMU registers occupy three pages in IO space. */
24 volatile unsigned long control; /* IOMMU control */
31 volatile unsigned long afsr; /* Async-fault status register */
32 volatile unsigned long afar; /* Async-fault physical address */
34 volatile unsigned long sbuscfg0; /* SBUS configuration registers, per-slot */
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/openbmc/linux/Documentation/misc-devices/
H A Duacce.rst1 .. SPDX-License-Identifier: GPL-2.0
4 ---------------------
6 Uacce (Unified/User-space-access-intended Accelerator Framework) targets to
14 IOMMU share the same CPU page tables and as a result the same translation
29 | MMU | | IOMMU |
42 ------------
44 Uacce is the kernel module, taking charge of iommu and address sharing.
47 The uacce device, built around the IOMMU SVA API, can access multiple
51 FIFO-like interface. And it maintains a unified address space between the
58 | WarpDrive library | ------------> | user driver |
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/openbmc/linux/drivers/iommu/
H A Dof_iommu.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * OF helpers for IOMMU
9 #include <linux/iommu.h>
26 struct fwnode_handle *fwnode = &iommu_spec->np->fwnode; in of_iommu_xlate()
30 if ((ops && !ops->of_xlate) || in of_iommu_xlate()
31 !of_device_is_available(iommu_spec->np)) in of_iommu_xlate()
34 ret = iommu_fwspec_init(dev, &iommu_spec->np->fwnode, ops); in of_iommu_xlate()
38 * The otherwise-empty fwspec handily serves to indicate the specific in of_iommu_xlate()
39 * IOMMU device we're waiting for, which will be useful if we ever get in of_iommu_xlate()
40 * a proper probe-ordering dependency mechanism in future. in of_iommu_xlate()
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H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
2 # The IOVA library may also be used by non-IOMMU_API users
11 bool "IOMMU Hardware Support"
22 menu "Generic IOMMU Pagetable Support"
36 sizes at both stage-1 and stage-2, as well as address spaces
37 up to 48-bits in size.
43 Enable self-tests for LPAE page table allocator. This performs
44 a series of page-table consistency checks during boot.
53 Enable support for the ARM Short-descriptor pagetable format.
54 This supports 32-bit virtual and physical addresses mapped using
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/openbmc/linux/Documentation/core-api/
H A Ddma-api-howto.rst10 with example pseudo-code. For a concise description of the API, see
11 DMA-API.txt.
13 CPU and DMA addresses
16 There are several kinds of addresses involved in the DMA API, and it's
19 The kernel normally uses virtual addresses. Any address returned by
24 addresses to CPU physical addresses, which are stored as "phys_addr_t" or
26 physical addresses. These are the addresses in /proc/iomem. The physical
32 memory, the addresses used by the device are bus addresses. In some
33 systems, bus addresses are identical to CPU physical addresses, but in
35 mappings between physical and bus addresses.
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/openbmc/linux/drivers/gpu/drm/amd/amdkfd/
H A Dkfd_flat_memory.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
3 * Copyright 2014-2022 Advanced Micro Devices, Inc.
44 * Access to ATC/IOMMU mapped memory w/ associated extension of VA to 48b
57 * System Unified Address - SUA
59 * The standard usage for GPU virtual addresses are that they are mapped by
67 * the operating system. This is via a technique and hardware called ATC/IOMMU.
81 * HSA64 - ATC/IOMMU 64b
90 * ATC/IOMMU, but it also has access to the GPUVM address space. The “system
98 * IOMMU path.
110 * ATC==1 means the 48b address is intended to be translated via IOMMU
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/openbmc/linux/arch/s390/include/asm/
H A Dpci.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #include <linux/iommu.h>
169 struct iommu_device iommu_dev; /* IOMMU core handle */
175 u64 start_dma; /* Start of available DMA addresses */
176 u64 end_dma; /* End of available DMA addresses */
193 /* IOMMU and passthrough */
194 struct s390_domain *s390_domain; /* s390 IOMMU domain data */
201 return (zdev->fh & (1UL << 31)) ? true : false; in zdev_enabled()
211 /* -----------------------------------------------------------------------------
213 ----------------------------------------------------------------------------- */
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/openbmc/qemu/docs/system/arm/
H A Dvirt.rst8 idiosyncrasies and limitations of a particular bit of real-world
16 ``virt-5.0`` machine type will behave like the ``virt`` machine from
17 the QEMU 5.0 release, and migration should work between ``virt-5.0``
18 of the 5.0 release and ``virt-5.0`` of the 5.1 release. Migration
20 the non-versioned ``virt`` machine type.
27 - PCI/PCIe devices
28 - Flash memory
29 - Either one or two PL011 UARTs for the NonSecure World
30 - An RTC
31 - The fw_cfg device that allows a guest to obtain data from QEMU
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/openbmc/linux/arch/x86/
H A DKconfig.debug1 # SPDX-License-Identifier: GPL-2.0
50 a full-blown printk console driver + klogd.
70 bool "Set upper limit of TLB entries to flush one-by-one"
73 X86-only for now.
76 kernel flushes one-by-one instead of doing a full TLB flush. In
79 to -1, the code flushes the whole TLB unconditionally. Otherwise,
88 bool "Enable IOMMU debugging"
92 Force the IOMMU to on even when you have less than 4GB of
94 allow to enable IOMMU leak tracing. Can be disabled at boot
95 time with iommu=noforce. This will also enable scatter gather
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/openbmc/linux/drivers/xen/
H A Dgrant-dma-ops.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Xen grant DMA-mapping layer - contains special DMA-mapping routines
4 * for providing grant references as DMA addresses to be used by frontends
11 #include <linux/dma-map-ops.h>
19 #include <xen/xen-ops.h>
72 * Used to act as a kind of software IOMMU for Xen guests by using grants as
73 * DMA addresses.
92 if (unlikely(data->broken)) in xen_grant_dma_alloc()
107 gnttab_grant_foreign_access_ref(grant + i, data->backend_domid, in xen_grant_dma_alloc()
127 if (unlikely(data->broken)) in xen_grant_dma_free()
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/openbmc/linux/arch/sparc/mm/
H A Diommu.c1 // SPDX-License-Identifier: GPL-2.0
3 * iommu.c: IOMMU specific routines for memory management.
15 #include <linux/dma-map-ops.h>
26 #include <asm/iommu.h>
60 struct iommu_struct *iommu; in sbus_iommu_init() local
67 iommu = kmalloc(sizeof(struct iommu_struct), GFP_KERNEL); in sbus_iommu_init()
68 if (!iommu) { in sbus_iommu_init()
69 prom_printf("Unable to allocate iommu structure\n"); in sbus_iommu_init()
73 iommu->regs = of_ioremap(&op->resource[0], 0, PAGE_SIZE * 3, in sbus_iommu_init()
75 if (!iommu->regs) { in sbus_iommu_init()
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/openbmc/linux/arch/parisc/include/asm/
H A Dpci.h1 /* SPDX-License-Identifier: GPL-2.0 */
11 ** (workstations 1-~4, servers 2-~32)
25 * accessing the PCI bus once #RESET is de-asserted.
26 * PCI spec somewhere says 1 second but with multi-PCI bus systems,
49 struct resource lmmio_space; /* bus addresses < 4Gb */
50 struct resource elmmio_space; /* additional bus addresses < 4Gb */
51 struct resource gmmio_space; /* bus addresses > 4Gb */
58 unsigned long lmmio_space_offset; /* CPU view - PCI view */
59 struct ioc *iommu; /* IOMMU this device is under */ member
60 /* REVISIT - spinlock to protect resources? */
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/openbmc/linux/arch/x86/kernel/
H A Damd_gart_64.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI.
6 * This allows to use PCI devices that only support 32bit addresses on systems
9 * See Documentation/core-api/dma-api-howto.rst for the interface specification.
29 #include <linux/iommu-helper.h>
34 #include <linux/dma-direct.h>
35 #include <linux/dma-map-ops.h>
38 #include <asm/iommu.h>
52 * If this is disabled the IOMMU will use an optimized flushing strategy
79 /* GART can only remap to physical addresses < 1TB */
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