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/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,usb-hsic-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-hsic-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm USB HSIC PHY Controller
10 - Bjorn Andersson <andersson@kernel.org>
11 - Vinod Koul <vkoul@kernel.org>
16 - enum:
17 - qcom,usb-hsic-phy-mdm9615
18 - qcom,usb-hsic-phy-msm8974
[all …]
H A Dallwinner,sun9i-a80-usb-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun9i-a80-usb-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
18 const: allwinner,sun9i-a80-usb-phy
21 maxItems: 1
25 - maxItems: 1
[all …]
H A Dmarvell,mmp3-hsic-phy.yaml1 # SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
4 ---
5 $id: http://devicetree.org/schemas/phy/marvell,mmp3-hsic-phy.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: Marvell MMP3 HSIC PHY
11 - Lubomir Rintel <lkundrak@v3.sk>
15 const: marvell,mmp3-hsic-phy
18 maxItems: 1
21 "#phy-cells":
25 - compatible
[all …]
H A Dnvidia,tegra186-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra186-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dnvidia,tegra124-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra124-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
H A Dnvidia,tegra210-xusb-padctl.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/nvidia,tegra210-xusb-padctl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
21 Some of the lanes are high-speed lanes, which can be used for PCIe, SATA or
22 super-speed USB. Other lanes are for various types of low-speed, full-speed
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
24 contains a software-configurable mux that sits between the I/O controller
[all …]
/openbmc/linux/Documentation/devicetree/bindings/mfd/
H A Domap-usb-host.txt5 - compatible: should be "ti,usbhs-host"
6 - reg: should contain one register range i.e. start and length
7 - ti,hwmods: must contain "usb_host_hs"
11 - num-ports: number of USB ports. Usually this is automatically detected
15 - portN-mode: String specifying the port mode for port N, where N can be
16 from 1 to 3. If the port mode is not specified, that port is treated
18 "ehci-phy",
19 "ehci-tll",
20 "ehci-hsic",
21 "ohci-phy-6pin-datse0",
[all …]
/openbmc/linux/drivers/phy/tegra/
H A Dxusb-tegra124.c1 // SPDX-License-Identifier: GPL-2.0-only
39 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 4) + 3))
46 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
47 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
48 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
49 #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_VCORE_DOWN(x) (1 << (18 + (x) * 4))
51 (1 << (17 + (x) * 4))
52 #define XUSB_PADCTL_ELPG_PROGRAM_SSPX_ELPG_CLAMP_EN(x) (1 << (16 + (x) * 4))
55 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
57 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
[all …]
H A Dxusb-tegra210.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved.
27 ((x) ? (11 + ((x) - 1) * 6) : 0)
51 #define XUSB_PADCTL_SS_PORT_MAP_PORTX_INTERNAL(x) (1 << (((x) * 5) + 4))
65 USB2_PORT_WAKEUP_EVENT(0) | USB2_PORT_WAKEUP_EVENT(1) | \
67 SS_PORT_WAKEUP_EVENT(0) | SS_PORT_WAKEUP_EVENT(1) | \
72 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_VCORE_DOWN (1 << 31)
73 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 30)
74 #define XUSB_PADCTL_ELPG_PROGRAM1_AUX_MUX_LP0_CLAMP_EN (1 << 29)
75 #define XUSB_PADCTL_ELPG_PROGRAM1_SSPX_ELPG_VCORE_DOWN(x) (1 << (2 + (x) * 3))
[all …]
H A Dxusb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2022, NVIDIA CORPORATION. All rights reserved.
31 if (args->args_count != 0) in tegra_xusb_pad_of_xlate()
32 return ERR_PTR(-EINVAL); in tegra_xusb_pad_of_xlate()
34 for (i = 0; i < pad->soc->num_lanes; i++) { in tegra_xusb_pad_of_xlate()
35 if (!pad->lanes[i]) in tegra_xusb_pad_of_xlate()
38 if (pad->lanes[i]->dev.of_node == args->np) { in tegra_xusb_pad_of_xlate()
39 phy = pad->lanes[i]; in tegra_xusb_pad_of_xlate()
45 phy = ERR_PTR(-ENODEV); in tegra_xusb_pad_of_xlate()
53 .compatible = "nvidia,tegra124-xusb-padctl",
[all …]
/openbmc/linux/drivers/phy/samsung/
H A Dphy-exynos5250-usb2.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 5250 support
13 #include "phy-samsung-usb2.h"
50 #define EXYNOS_5250_HOSTPHYCTRL0_LINKSWRST BIT(1)
88 #define EXYNOS_5250_HOSTEHCICTRL_FLADJVALHOST_SHIFT 1
95 #define EXYNOS_5250_HOSTOHCICTRL_FRAMELENVAL_SHIFT 1
115 #define EXYNOS_5250_USBOTGSYS_SIDDQ_UOTG BIT(1)
126 #define EXYNOS_5250_MODE_SWITCH_MASK 1
128 #define EXYNOS_5250_MODE_SWITCH_HOST 1
168 return -EINVAL; in exynos5250_rate_to_clk()
[all …]
/openbmc/linux/drivers/phy/marvell/
H A Dphy-pxa-28nm-hsic.c1 // SPDX-License-Identifier: GPL-2.0-only
38 #define PHY_28NM_HSIC_CONNECT_INT BIT(1)
59 struct platform_device *pdev = mv_phy->pdev; in mv_hsic_phy_init()
60 void __iomem *base = mv_phy->base; in mv_hsic_phy_init()
63 clk_prepare_enable(mv_phy->clk); in mv_hsic_phy_init()
80 dev_err(&pdev->dev, "HSIC PHY PLL not locked after 100mS."); in mv_hsic_phy_init()
81 clk_disable_unprepare(mv_phy->clk); in mv_hsic_phy_init()
90 struct platform_device *pdev = mv_phy->pdev; in mv_hsic_phy_power_on()
91 void __iomem *base = mv_phy->base; in mv_hsic_phy_power_on()
98 reg |= PHY_28NM_HSIC_S2H_HSIC_EN; /* Enable HSIC PHY */ in mv_hsic_phy_power_on()
[all …]
/openbmc/linux/drivers/usb/chipidea/
H A Dci_hdrc_imx.h1 /* SPDX-License-Identifier: GPL-2.0+ */
13 unsigned int disable_oc:1; /* over current detect disabled */
15 /* true if over-current polarity is active low */
16 unsigned int oc_pol_active_low:1;
19 unsigned int oc_pol_configured:1;
21 unsigned int pwr_pol:1; /* power polarity */
22 unsigned int evdo:1; /* set external vbus divider option */
23 unsigned int ulpi:1; /* connected to an ULPI phy */
24 unsigned int hsic:1; /* HSIC controller */ member
25 unsigned int ext_id:1; /* ID from exteranl event */
[all …]
H A Dusbmisc_imx.c1 // SPDX-License-Identifier: GPL-2.0+
65 #define MX6_BM_NON_BURST_SETTING BIT(1)
79 /* set before portsc.suspendM = 1 */
81 /* HSIC enable */
83 /* Force HSIC module 480M clock on, even when in Host is in suspend mode */
87 /* For imx6dql, it is host-only controller, for later imx6, it is otg's */
91 #define MX6SX_USB_VBUS_WAKEUP_SOURCE_AVALID MX6SX_USB_VBUS_WAKEUP_SOURCE(1)
101 #define MX7D_USB_VBUS_WAKEUP_SOURCE_AVALID MX7D_USB_VBUS_WAKEUP_SOURCE(1)
105 /* The default DM/DP value is pull-down */
107 #define MX7D_USBNC_USB_CTRL2_OPMODE_NON_DRIVING MX7D_USBNC_USB_CTRL2_OPMODE(1)
[all …]
H A Dci_hdrc_msm.c1 // SPDX-License-Identifier: GPL-2.0
13 #include <linux/reset-controller.h>
44 bool hsic; member
52 void __iomem *addr = ci_msm->base; in ci_hdrc_msm_por_reset()
81 struct device *dev = ci->dev->parent; in ci_hdrc_msm_notify_event()
90 if (msm_ci->secondary_phy) { in ci_hdrc_msm_notify_event()
91 u32 val = readl_relaxed(msm_ci->base + HS_PHY_SEC_CTRL); in ci_hdrc_msm_notify_event()
93 writel_relaxed(val, msm_ci->base + HS_PHY_SEC_CTRL); in ci_hdrc_msm_notify_event()
96 ret = phy_init(ci->phy); in ci_hdrc_msm_notify_event()
100 ret = phy_power_on(ci->phy); in ci_hdrc_msm_notify_event()
[all …]
H A Dci_hdrc_imx.c1 // SPDX-License-Identifier: GPL-2.0+
81 { .compatible = "fsl,imx23-usb", .data = &imx23_usb_data},
82 { .compatible = "fsl,imx28-usb", .data = &imx28_usb_data},
83 { .compatible = "fsl,imx27-usb", .data = &imx27_usb_data},
84 { .compatible = "fsl,imx6q-usb", .data = &imx6q_usb_data},
85 { .compatible = "fsl,imx6sl-usb", .data = &imx6sl_usb_data},
86 { .compatible = "fsl,imx6sx-usb", .data = &imx6sx_usb_data},
87 { .compatible = "fsl,imx6ul-usb", .data = &imx6ul_usb_data},
88 { .compatible = "fsl,imx7d-usb", .data = &imx7d_usb_data},
89 { .compatible = "fsl,imx7ulp-usb", .data = &imx7ulp_usb_data},
[all …]
/openbmc/linux/drivers/pinctrl/tegra/
H A Dpinctrl-tegra-xusb.c1 // SPDX-License-Identifier: GPL-2.0-only
20 #include <dt-bindings/pinctrl/pinctrl-tegra-xusb.h>
23 #include "../pinctrl-utils.h"
26 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_VCORE_DOWN (1 << 26)
27 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN_EARLY (1 << 25)
28 #define XUSB_PADCTL_ELPG_PROGRAM_AUX_MUX_LP0_CLAMP_EN (1 << 24)
31 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL0_LOCKDET (1 << 19)
33 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL1_PLL_RST (1 << 1)
36 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_REFCLKBUF_EN (1 << 6)
37 #define XUSB_PADCTL_IOPHY_PLL_P0_CTL2_TXCLKREF_EN (1 << 5)
[all …]
/openbmc/linux/drivers/clk/sunxi-ng/
H A Dccu-sun9i-a80-usb.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2016 Chen-Yu Tsai. All rights reserved.
7 #include <linux/clk-provider.h>
15 #include "ccu-sun9i-a80-usb.h"
25 static SUNXI_CCU_GATE_DATA(bus_hci0_clk, "bus-hci0", clk_parent_bus, 0x0, BIT(1), 0);
26 static SUNXI_CCU_GATE_DATA(usb_ohci0_clk, "usb-ohci0", clk_parent_hosc, 0x0, BIT(2), 0);
27 static SUNXI_CCU_GATE_DATA(bus_hci1_clk, "bus-hci1", clk_parent_bus, 0x0, BIT(3), 0);
28 static SUNXI_CCU_GATE_DATA(bus_hci2_clk, "bus-hci2", clk_parent_bus, 0x0, BIT(5), 0);
29 static SUNXI_CCU_GATE_DATA(usb_ohci2_clk, "usb-ohci2", clk_parent_hosc, 0x0, BIT(6), 0);
31 static SUNXI_CCU_GATE_DATA(usb0_phy_clk, "usb0-phy", clk_parent_hosc, 0x4, BIT(1), 0);
[all …]
/openbmc/linux/drivers/gpu/drm/bridge/
H A Dsil-sii8620.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 * Copyright (C) 2013-2014 Silicon Image, Inc.
33 /* System Control #1, default value: 0x00 */
41 #define BIT_SYS_CTRL1_TX_CTRL_HDMI BIT(1)
52 #define BIT_DPD_PD_MHL_CLK_N BIT(1)
62 #define BIT_DCTL_HSIC_TX_BIST_START_SEL BIT(1)
73 #define BIT_PWD_SRST_HDCP2X_SW_RST BIT(1)
79 /* Video H Resolution #1, default value: 0x00 */
128 #define BIT_CTRL1_GPIO_I_6 BIT(1)
135 #define BIT_INT_CTRL_INTR_POLARITY BIT(1)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,msm8974-pinctrl.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,msm8974-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
18 const: qcom,msm8974-pinctrl
21 maxItems: 1
24 maxItems: 1
26 interrupt-controller: true
[all …]
H A Dnvidia,tegra124-xusb-padctl.txt7 needed for USB. For the new binding, see ../phy/nvidia,tegra-xusb-padctl.txt.
14 This document defines the device-specific binding for the XUSB pad controller.
16 Refer to pinctrl-bindings.txt in this directory for generic information about
17 pin controller device tree bindings and ../phy/phy-bindings.txt for details on
21 --------------------
22 - compatible: For Tegra124, must contain "nvidia,tegra124-xusb-padctl".
23 Otherwise, must contain '"nvidia,<chip>-xusb-padctl",
24 "nvidia-tegra124-xusb-padctl"', where <chip> is tegra132 or tegra210.
25 - reg: Physical base address and length of the controller's registers.
26 - resets: Must contain an entry for each entry in reset-names.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dci-hdrc-usb2.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/ci-hdrc-usb2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xu Yang <xu.yang_2@nxp.com>
11 - Peng Fan <peng.fan@nxp.com>
16 - enum:
17 - chipidea,usb2
18 - lsi,zevio-usb
19 - nuvoton,npcm750-udc
[all …]
H A Dnvidia,tegra124-xusb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/usb/nvidia,tegra124-xusb.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
20 - description: NVIDIA Tegra124
21 const: nvidia,tegra124-xusb
23 - description: NVIDIA Tegra132
25 - const: nvidia,tegra132-xusb
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-sunxi/
H A Dclock_sun50i_h6.h6 * SPDX-License-Identifier: GPL-2.0+
31 u32 pll9_cfg; /* 0x070 pll9 (hsic) control */
52 u32 pll9_pat0; /* 0x170 pll9 (hsic) pattern0 */
53 u32 pll9_pat1; /* 0x174 pll9 (hsic) pattern1 */
75 u32 pll9_bias; /* 0x370 pll9 (hsic) bias */
239 #define CCM_PLL5_CTRL_DIV2(div0) ((div0) << 1)
249 #define CCM_PLL6_CTRL_DIV2_SHIFT 1
281 #define APB2_CLK_RATE_M(m) (((m)-1) << 0)
289 #define MBUS_CLK_SRC_PLL6X2 (1 << 24)
292 #define MBUS_CLK_M(m) (((m)-1) << 0)
[all …]
/openbmc/linux/drivers/phy/allwinner/
H A Dphy-sun9i-usb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2014-2015 Chen-Yu Tsai <wens@csie.org>
7 * Based on phy-sun4i-usb.c from
29 /* usb1 HSIC specific bits */
33 #define SUNXI_HSIC BIT(1)
52 if (phy->type == USBPHY_INTERFACE_MODE_HSIC) in sun9i_usb_phy_passby()
56 reg_value = readl(phy->pmu); in sun9i_usb_phy_passby()
63 writel(reg_value, phy->pmu); in sun9i_usb_phy_passby()
71 ret = clk_prepare_enable(phy->clk); in sun9i_usb_phy_init()
75 ret = clk_prepare_enable(phy->hsic_clk); in sun9i_usb_phy_init()
[all …]

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