Searched +full:gsbi +full:- +full:v1 (Results 1 – 11 of 11) sorted by relevance
/openbmc/linux/Documentation/devicetree/bindings/soc/qcom/ |
H A D | qcom,gsbi.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/soc/qcom/qcom,gsbi.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Qualcomm General Serial Bus Interface (GSBI) 10 - Andy Gross <agross@kernel.org> 11 - Bjorn Andersson <bjorn.andersson@linaro.org> 12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 15 The GSBI controller is modeled as a node with zero or more child nodes, each 16 representing a serial sub-node device that is mux'd as part of the GSBI [all …]
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/openbmc/linux/arch/arm/boot/dts/qcom/ |
H A D | qcom-msm8660.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/interrupt-controller/irq.h> 5 #include <dt-bindings/interrupt-controller/arm-gic.h> 6 #include <dt-bindings/clock/qcom,gcc-msm8660.h> 7 #include <dt-bindings/soc/qcom,gsbi.h> 10 #address-cells = <1>; 11 #size-cells = <1>; 14 interrupt-parent = <&intc>; 17 #address-cells = <1>; [all …]
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H A D | qcom-mdm9615.dtsi | 1 // SPDX-License-Identifier: GPL-2.0+ OR MIT 9 /dts-v1/; 11 #include <dt-bindings/interrupt-controller/arm-gic.h> 12 #include <dt-bindings/clock/qcom,gcc-mdm9615.h> 13 #include <dt-bindings/clock/qcom,lcc-msm8960.h> 14 #include <dt-bindings/reset/qcom,gcc-mdm9615.h> 15 #include <dt-bindings/mfd/qcom-rpm.h> 16 #include <dt-bindings/soc/qcom,gsbi.h> 19 #address-cells = <1>; 20 #size-cells = <1>; [all …]
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H A D | qcom-msm8960.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/interrupt-controller/arm-gic.h> 5 #include <dt-bindings/clock/qcom,gcc-msm8960.h> 6 #include <dt-bindings/reset/qcom,gcc-msm8960.h> 7 #include <dt-bindings/clock/qcom,lcc-msm8960.h> 8 #include <dt-bindings/mfd/qcom-rpm.h> 9 #include <dt-bindings/soc/qcom,gsbi.h> 12 #address-cells = <1>; 13 #size-cells = <1>; [all …]
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H A D | qcom-ipq8064.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/interrupt-controller/arm-gic.h> 5 #include <dt-bindings/mfd/qcom-rpm.h> 6 #include <dt-bindings/clock/qcom,rpmcc.h> 7 #include <dt-bindings/clock/qcom,gcc-ipq806x.h> 8 #include <dt-bindings/clock/qcom,lcc-ipq806x.h> 9 #include <dt-bindings/gpio/gpio.h> 10 #include <dt-bindings/reset/qcom,gcc-ipq806x.h> 11 #include <dt-bindings/soc/qcom,gsbi.h> [all …]
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H A D | qcom-apq8064.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 /dts-v1/; 4 #include <dt-bindings/clock/qcom,gcc-msm8960.h> 5 #include <dt-bindings/clock/qcom,lcc-msm8960.h> 6 #include <dt-bindings/reset/qcom,gcc-msm8960.h> 7 #include <dt-bindings/clock/qcom,mmcc-msm8960.h> 8 #include <dt-bindings/clock/qcom,rpmcc.h> 9 #include <dt-bindings/soc/qcom,gsbi.h> 10 #include <dt-bindings/interrupt-controller/irq.h> 11 #include <dt-bindings/interrupt-controller/arm-gic.h> [all …]
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H A D | qcom-ipq8064-v1.0.dtsi | 1 // SPDX-License-Identifier: GPL-2.0 2 #include "qcom-ipq8064.dtsi" 3 #include <dt-bindings/input/input.h> 4 #include <dt-bindings/leds/common.h> 7 model = "Qualcomm Technologies, Inc. IPQ8064-v1.0"; 14 stdout-path = "serial0:115200n8"; 18 gsbi@16300000 { 27 gsbi5: gsbi@1a200000 { 34 pinctrl-0 = <&spi_pins>; 35 pinctrl-names = "default"; [all …]
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H A D | qcom-ipq8064-ap148.dts | 1 // SPDX-License-Identifier: GPL-2.0 2 #include "qcom-ipq8064-v1.0.dtsi" 5 model = "Qualcomm Technologies, Inc. IPQ8064/AP-148"; 6 compatible = "qcom,ipq8064-ap148", "qcom,ipq8064"; 13 drive-strength = <2>; 14 bias-pull-up; 19 gsbi@16300000 { 22 clock-frequency = <200000>; 23 pinctrl-0 = <&i2c4_pins>; 24 pinctrl-names = "default";
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/openbmc/linux/drivers/soc/qcom/ |
H A D | qcom_gsbi.c | 1 // SPDX-License-Identifier: GPL-2.0-only 15 #include <dt-bindings/soc/qcom,gsbi.h> 83 { /* ADM 0 - B */ 88 { /* ADM 0 - B */ 93 { /* ADM 1 - A */ 98 { /* ADM 1 - B */ 118 { .compatible = "qcom,tcsr-ipq8064", .data = &config_ipq8064}, 119 { .compatible = "qcom,tcsr-apq8064", .data = &config_apq8064}, 120 { .compatible = "qcom,tcsr-msm8960", .data = &config_msm8960}, 121 { .compatible = "qcom,tcsr-msm8660", .data = &config_msm8660}, [all …]
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/openbmc/linux/Documentation/devicetree/bindings/serial/ |
H A D | qcom,msm-uartdm.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 3 --- 4 $id: http://devicetree.org/schemas/serial/qcom,msm-uartdm.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Andy Gross <agross@kernel.org> 11 - Bjorn Andersson <bjorn.andersson@linaro.org> 12 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 15 The MSM serial UARTDM hardware is designed for high-speed use cases where the 16 transmit and/or receive channels can be offloaded to a dma-engine. From a 28 - enum: [all …]
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/openbmc/linux/ |
H A D | opengrok1.0.log | 1 2024-12-28 20:07:11.902-0600 FINER t583 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' 2 2024-12-28 20:07:11.913-0600 FINEST t583 Statistics.logIt: Added: '/openbmc/linux/drivers/net/ethernet/marvell/mvpp2/mvpp2_prs.c' (CAnalyzer) (took 116 ms) 3 2024-12-28 20:07:11.899-0600 FINER t593 IndexDatabase.createAnnotationCache: failed to create annotation: repository {dir='/opengrok/src/openbmc/linux',type=git,historyCache=on,renamed=false,merge=true,annotationCache=off} does not allow to create annotation cache for '/opengrok/src/openbmc/linux/tools/testing/selftests/powerpc/tm/tm-signa [all...] |