1*0557dc5eSKrzysztof Kozlowski# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause 2*0557dc5eSKrzysztof Kozlowski%YAML 1.2 3*0557dc5eSKrzysztof Kozlowski--- 4*0557dc5eSKrzysztof Kozlowski$id: http://devicetree.org/schemas/soc/qcom/qcom,gsbi.yaml# 5*0557dc5eSKrzysztof Kozlowski$schema: http://devicetree.org/meta-schemas/core.yaml# 6*0557dc5eSKrzysztof Kozlowski 7*0557dc5eSKrzysztof Kozlowskititle: Qualcomm General Serial Bus Interface (GSBI) 8*0557dc5eSKrzysztof Kozlowski 9*0557dc5eSKrzysztof Kozlowskimaintainers: 10*0557dc5eSKrzysztof Kozlowski - Andy Gross <agross@kernel.org> 11*0557dc5eSKrzysztof Kozlowski - Bjorn Andersson <bjorn.andersson@linaro.org> 12*0557dc5eSKrzysztof Kozlowski - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> 13*0557dc5eSKrzysztof Kozlowski 14*0557dc5eSKrzysztof Kozlowskidescription: 15*0557dc5eSKrzysztof Kozlowski The GSBI controller is modeled as a node with zero or more child nodes, each 16*0557dc5eSKrzysztof Kozlowski representing a serial sub-node device that is mux'd as part of the GSBI 17*0557dc5eSKrzysztof Kozlowski configuration settings. The mode setting will govern the input/output mode 18*0557dc5eSKrzysztof Kozlowski of the 4 GSBI IOs. 19*0557dc5eSKrzysztof Kozlowski 20*0557dc5eSKrzysztof Kozlowski A GSBI controller node can contain 0 or more child nodes representing serial 21*0557dc5eSKrzysztof Kozlowski devices. These serial devices can be a QCOM UART, I2C controller, spi 22*0557dc5eSKrzysztof Kozlowski controller, or some combination of aforementioned devices. 23*0557dc5eSKrzysztof Kozlowski 24*0557dc5eSKrzysztof Kozlowskiproperties: 25*0557dc5eSKrzysztof Kozlowski compatible: 26*0557dc5eSKrzysztof Kozlowski const: qcom,gsbi-v1.0.0 27*0557dc5eSKrzysztof Kozlowski 28*0557dc5eSKrzysztof Kozlowski '#address-cells': 29*0557dc5eSKrzysztof Kozlowski const: 1 30*0557dc5eSKrzysztof Kozlowski 31*0557dc5eSKrzysztof Kozlowski cell-index: 32*0557dc5eSKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/uint32 33*0557dc5eSKrzysztof Kozlowski description: 34*0557dc5eSKrzysztof Kozlowski The GSBI index. 35*0557dc5eSKrzysztof Kozlowski 36*0557dc5eSKrzysztof Kozlowski clocks: 37*0557dc5eSKrzysztof Kozlowski maxItems: 1 38*0557dc5eSKrzysztof Kozlowski 39*0557dc5eSKrzysztof Kozlowski clock-names: 40*0557dc5eSKrzysztof Kozlowski const: iface 41*0557dc5eSKrzysztof Kozlowski 42*0557dc5eSKrzysztof Kozlowski qcom,crci: 43*0557dc5eSKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/uint32 44*0557dc5eSKrzysztof Kozlowski description: 45*0557dc5eSKrzysztof Kozlowski CRCI MUX value for QUP CRCI ports. Please reference 46*0557dc5eSKrzysztof Kozlowski include/dt-bindings/soc/qcom,gsbi.h for valid CRCI mux values. 47*0557dc5eSKrzysztof Kozlowski 48*0557dc5eSKrzysztof Kozlowski qcom,mode: 49*0557dc5eSKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/uint32 50*0557dc5eSKrzysztof Kozlowski description: 51*0557dc5eSKrzysztof Kozlowski MUX value for configuration of the serial interface. Please reference 52*0557dc5eSKrzysztof Kozlowski include/dt-bindings/soc/qcom,gsbi.h for valid mux values. 53*0557dc5eSKrzysztof Kozlowski 54*0557dc5eSKrzysztof Kozlowski '#size-cells': 55*0557dc5eSKrzysztof Kozlowski const: 1 56*0557dc5eSKrzysztof Kozlowski 57*0557dc5eSKrzysztof Kozlowski syscon-tcsr: 58*0557dc5eSKrzysztof Kozlowski $ref: /schemas/types.yaml#/definitions/phandle 59*0557dc5eSKrzysztof Kozlowski description: 60*0557dc5eSKrzysztof Kozlowski Phandle of TCSR syscon node.Required if child uses dma. 61*0557dc5eSKrzysztof Kozlowski 62*0557dc5eSKrzysztof Kozlowski ranges: true 63*0557dc5eSKrzysztof Kozlowski 64*0557dc5eSKrzysztof Kozlowski reg: 65*0557dc5eSKrzysztof Kozlowski maxItems: 1 66*0557dc5eSKrzysztof Kozlowski 67*0557dc5eSKrzysztof KozlowskipatternProperties: 68*0557dc5eSKrzysztof Kozlowski "spi@[0-9a-f]+$": 69*0557dc5eSKrzysztof Kozlowski type: object 70*0557dc5eSKrzysztof Kozlowski $ref: /schemas/spi/qcom,spi-qup.yaml# 71*0557dc5eSKrzysztof Kozlowski 72*0557dc5eSKrzysztof Kozlowski "i2c@[0-9a-f]+$": 73*0557dc5eSKrzysztof Kozlowski type: object 74*0557dc5eSKrzysztof Kozlowski $ref: /schemas/i2c/qcom,i2c-qup.yaml# 75*0557dc5eSKrzysztof Kozlowski 76*0557dc5eSKrzysztof Kozlowski "serial@[0-9a-f]+$": 77*0557dc5eSKrzysztof Kozlowski type: object 78*0557dc5eSKrzysztof Kozlowski $ref: /schemas/serial/qcom,msm-uartdm.yaml# 79*0557dc5eSKrzysztof Kozlowski 80*0557dc5eSKrzysztof Kozlowskirequired: 81*0557dc5eSKrzysztof Kozlowski - compatible 82*0557dc5eSKrzysztof Kozlowski - cell-index 83*0557dc5eSKrzysztof Kozlowski - clocks 84*0557dc5eSKrzysztof Kozlowski - clock-names 85*0557dc5eSKrzysztof Kozlowski - qcom,mode 86*0557dc5eSKrzysztof Kozlowski - reg 87*0557dc5eSKrzysztof Kozlowski 88*0557dc5eSKrzysztof KozlowskiadditionalProperties: false 89*0557dc5eSKrzysztof Kozlowski 90*0557dc5eSKrzysztof Kozlowskiexamples: 91*0557dc5eSKrzysztof Kozlowski - | 92*0557dc5eSKrzysztof Kozlowski #include <dt-bindings/clock/qcom,gcc-msm8960.h> 93*0557dc5eSKrzysztof Kozlowski #include <dt-bindings/interrupt-controller/arm-gic.h> 94*0557dc5eSKrzysztof Kozlowski #include <dt-bindings/soc/qcom,gsbi.h> 95*0557dc5eSKrzysztof Kozlowski 96*0557dc5eSKrzysztof Kozlowski gsbi@12440000 { 97*0557dc5eSKrzysztof Kozlowski compatible = "qcom,gsbi-v1.0.0"; 98*0557dc5eSKrzysztof Kozlowski reg = <0x12440000 0x100>; 99*0557dc5eSKrzysztof Kozlowski cell-index = <1>; 100*0557dc5eSKrzysztof Kozlowski clocks = <&gcc GSBI1_H_CLK>; 101*0557dc5eSKrzysztof Kozlowski clock-names = "iface"; 102*0557dc5eSKrzysztof Kozlowski #address-cells = <1>; 103*0557dc5eSKrzysztof Kozlowski #size-cells = <1>; 104*0557dc5eSKrzysztof Kozlowski ranges; 105*0557dc5eSKrzysztof Kozlowski 106*0557dc5eSKrzysztof Kozlowski syscon-tcsr = <&tcsr>; 107*0557dc5eSKrzysztof Kozlowski qcom,mode = <GSBI_PROT_I2C_UART>; 108*0557dc5eSKrzysztof Kozlowski 109*0557dc5eSKrzysztof Kozlowski serial@12450000 { 110*0557dc5eSKrzysztof Kozlowski compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm"; 111*0557dc5eSKrzysztof Kozlowski reg = <0x12450000 0x100>, 112*0557dc5eSKrzysztof Kozlowski <0x12400000 0x03>; 113*0557dc5eSKrzysztof Kozlowski interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>; 114*0557dc5eSKrzysztof Kozlowski clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>; 115*0557dc5eSKrzysztof Kozlowski clock-names = "core", "iface"; 116*0557dc5eSKrzysztof Kozlowski }; 117*0557dc5eSKrzysztof Kozlowski 118*0557dc5eSKrzysztof Kozlowski i2c@12460000 { 119*0557dc5eSKrzysztof Kozlowski compatible = "qcom,i2c-qup-v1.1.1"; 120*0557dc5eSKrzysztof Kozlowski reg = <0x12460000 0x1000>; 121*0557dc5eSKrzysztof Kozlowski pinctrl-0 = <&i2c1_pins>; 122*0557dc5eSKrzysztof Kozlowski pinctrl-1 = <&i2c1_pins_sleep>; 123*0557dc5eSKrzysztof Kozlowski pinctrl-names = "default", "sleep"; 124*0557dc5eSKrzysztof Kozlowski interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>; 125*0557dc5eSKrzysztof Kozlowski clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>; 126*0557dc5eSKrzysztof Kozlowski clock-names = "core", "iface"; 127*0557dc5eSKrzysztof Kozlowski #address-cells = <1>; 128*0557dc5eSKrzysztof Kozlowski #size-cells = <0>; 129*0557dc5eSKrzysztof Kozlowski 130*0557dc5eSKrzysztof Kozlowski status = "disabled"; /* UART chosen */ 131*0557dc5eSKrzysztof Kozlowski }; 132*0557dc5eSKrzysztof Kozlowski }; 133