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Searched +full:gpio +full:- +full:wo +full:- +full:state (Results 1 – 25 of 27) sorted by relevance

12

/openbmc/u-boot/drivers/gpio/
H A Dzynq_gpio.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Xilinx Zynq GPIO device driver
7 * Most of code taken from linux kernel driver (linux/drivers/gpio/gpio-zynq.c)
8 * Copyright (C) 2009 - 2014 Xilinx, Inc.
12 #include <asm/gpio.h>
44 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
47 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
50 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
53 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
56 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
[all …]
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dqcom,sm8450-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8450-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20 const: qcom,sm8450-tlmm
28 interrupt-controller: true
29 "#interrupt-cells": true
30 gpio-controller: true
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H A Dqcom,sdx75-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sdx75-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rohit Agarwal <quic_rohiagar@quicinc.com>
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20 const: qcom,sdx75-tlmm
26 interrupt-controller: true
27 "#interrupt-cells": true
28 gpio-controller: true
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H A Dqcom,msm8909-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,msm8909-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Stephan Gerhold <stephan@gerhold.net>
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20 const: qcom,msm8909-tlmm
28 interrupt-controller: true
29 "#interrupt-cells": true
30 gpio-controller: true
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H A Dqcom,sm7150-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm7150-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <andersson@kernel.org>
11 - Danila Tikhonov <danila@jiaxyga.com>
17 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
21 const: qcom,sm7150-tlmm
26 reg-names:
28 - const: west
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H A Dqcom,sm8350-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8350-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vinod Koul <vkoul@kernel.org>
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20 const: qcom,sm8350-tlmm
28 interrupt-controller: true
29 "#interrupt-cells": true
30 gpio-controller: true
[all …]
H A Dqcom,sm8550-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm8550-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Abel Vesa <abel.vesa@linaro.org>
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20 const: qcom,sm8550-tlmm
26 interrupt-controller: true
27 "#interrupt-cells": true
28 gpio-controller: true
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H A Dqcom,sc8180x-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc8180x-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20 const: qcom,sc8180x-tlmm
25 reg-names:
27 - const: west
28 - const: east
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H A Dqcom,sc8280xp-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sc8280xp-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Bjorn Andersson <bjorn.andersson@linaro.org>
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20 const: qcom,sc8280xp-tlmm
28 interrupt-controller: true
29 "#interrupt-cells": true
30 gpio-controller: true
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H A Dqcom,sm6375-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm6375-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Konrad Dybcio <konrad.dybcio@somainline.org>
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20 const: qcom,sm6375-tlmm
28 interrupt-controller: true
29 "#interrupt-cells": true
30 gpio-controller: true
[all …]
H A Dqcom,sm6350-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm6350-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Konrad Dybcio <konrad.dybcio@somainline.org>
16 - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
20 const: qcom,sm6350-tlmm
29 interrupt-controller: true
30 "#interrupt-cells": true
31 gpio-controller: true
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H A Dqcom,sdx65-tlmm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sdx65-tlmm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vamsi krishna Lanka <quic_vamslank@quicinc.com>
17 const: qcom,sdx65-tlmm
25 interrupt-controller: true
26 "#interrupt-cells": true
27 gpio-controller: true
28 "#gpio-cells": true
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/openbmc/linux/drivers/gpio/
H A Dgpio-zynq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Xilinx Zynq GPIO device driver
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
10 #include <linux/gpio/driver.h>
20 #define DRIVER_NAME "zynq-gpio"
46 ZYNQ##str##_GPIO_BANK0_NGPIO - 1)
49 ZYNQ##str##_GPIO_BANK1_NGPIO - 1)
52 ZYNQ##str##_GPIO_BANK2_NGPIO - 1)
55 ZYNQ##str##_GPIO_BANK3_NGPIO - 1)
58 ZYNQ##str##_GPIO_BANK4_NGPIO - 1)
[all …]
/openbmc/linux/drivers/media/pci/cx88/
H A Dcx88-reg.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * cx88x-hw.h - CX2388x register offsets
5 * Copyright (C) 1996,97,98 Ralph Metzler (rjkm@thp.uni-koeln.de)
92 // DMA Channels 1-6 belong to SPIPE
96 // DMA Channels 9-20 belong to SPIPE
202 #define MO_VIDY_GPCNTRL 0x31C030 // {2}WO Video Y general purpose control
203 #define MO_VIDU_GPCNTRL 0x31C034 // {2}WO Video U general purpose control
204 #define MO_VIDV_GPCNTRL 0x31C038 // {2}WO Video V general purpose control
205 #define MO_VBI_GPCNTRL 0x31C03C // {2}WO VBI general purpose counter
219 #define MO_AUDD_GPCNTRL 0x32C030 // {2}WO Audio down general purpose control
[all …]
/openbmc/linux/drivers/spi/
H A Dspi-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2008 - 2014 Xilinx, Inc.
7 * based on Blackfin On-Chip SPI Driver (spi_bfin5xx.c)
12 #include <linux/gpio/consumer.h>
24 #define CDNS_SPI_NAME "cdns-spi"
29 #define CDNS_SPI_IER 0x08 /* Interrupt Enable Register, WO */
30 #define CDNS_SPI_IDR 0x0c /* Interrupt Disable Register, WO */
34 #define CDNS_SPI_TXD 0x1C /* Data Transmit Register, WO */
62 * SPI Configuration Register - Baud rate and target select
101 * struct cdns_spi - This definition defines spi driver instance
[all …]
/openbmc/linux/drivers/net/ethernet/mellanox/mlxsw/
H A Dreg.h1 /* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0 */
2 /* Copyright (c) 2015-2018 Mellanox Technologies. All rights reserved */
29 #define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
30 #define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
32 /* SGCR - Switch General Configuration Register
33 * --------------------------------------------
55 /* SPAD - Switch Physical Address Register
56 * ---------------------------------------
72 /* SSPR - Switch System Port Record Register
73 * -----------------------------------------
[all …]
/openbmc/linux/drivers/tty/serial/
H A Dmxs-auart.c1 // SPDX-License-Identifier: GPL-2.0+
9 * Copyright 2014 Oleksij Rempel <linux@rempel-privat.de>
11 * Copyright 2008-2010 Freescale Semiconductor, Inc.
34 #include <linux/dma-mapping.h>
37 #include <linux/gpio/consumer.h>
90 #define AUART_LINECTRL_WLEN(v) ((((v) - 5) & 0x3) << 5)
138 * RW. Receive Timeout Counter Value: number of 8-bit-time to wait before
140 * input is idle, then the watchdog counter will decrement each bit-time. Note
141 * 7-bit-time is added to the programmed value, so a value of zero will set
142 * the counter to 7-bit-time, a value of 0x1 gives 15-bit-time and so on. Also
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H A Dmax310x.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Copyright (C) 2012-2016 Alexander Shiyan <shc_work@mail.ru>
16 #include <linux/gpio/driver.h>
61 #define MAX310X_GPIOCFG_REG (0x18) /* GPIO config */
62 #define MAX310X_GPIODATA_REG (0x19) /* GPIO data */
73 #define MAX310X_GLOBALCMD_REG MAX310X_REG_1F /* Global Command (WO) */
96 #define MAX310X_LSR_CTS_BIT (1 << 7) /* CTS pin state */
104 #define MAX310X_SPCHR_MULTIDROP_BIT (1 << 5) /* 9-bit multidrop addr char */
107 #define MAX310X_STS_GPIO0_BIT (1 << 0) /* GPIO 0 interrupt */
108 #define MAX310X_STS_GPIO1_BIT (1 << 1) /* GPIO 1 interrupt */
[all …]
/openbmc/linux/drivers/media/usb/dvb-usb-v2/
H A Dmxl111sf.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2010-2014 Michael Krufky (mkrufky@linuxtv.org)
5 * see Documentation/driver-api/media/drivers/dvb-usb.rst for more information
13 #include "mxl111sf-reg.h"
14 #include "mxl111sf-phy.h"
15 #include "mxl111sf-i2c.h"
16 #include "mxl111sf-gpio.h"
18 #include "mxl111sf-demod.h"
19 #include "mxl111sf-tuner.h"
26 MODULE_PARM_DESC(debug, "set debugging level (1=info, 2=xfer, 4=i2c, 8=reg, 16=adv (or-able)).");
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/openbmc/linux/drivers/i2c/busses/
H A Di2c-cadence.c1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright (C) 2009 - 2014 Xilinx, Inc.
30 #define CDNS_I2C_IER_OFFSET 0x24 /* IRQ Enable Register, WO */
31 #define CDNS_I2C_IDR_OFFSET 0x28 /* IRQ Disable Register, WO */
121 #define CDNS_I2C_TRANSFER_SIZE(max) ((max) - 3)
123 #define DRIVER_NAME "cdns-i2c"
134 #define cdns_i2c_readreg(offset) readl_relaxed(id->membase + offset)
135 #define cdns_i2c_writereg(val, offset) writel_relaxed(val, id->membase + offset)
139 * enum cdns_i2c_mode - I2C Controller current operating mode
150 * enum cdns_i2c_slave_state - Slave state when I2C is operating in slave mode
[all …]
/openbmc/linux/drivers/iio/adc/
H A Dad7192.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 2011-2015 Analog Devices Inc.
32 #define AD7192_REG_COMM 0 /* Communications Register (WO, 8-bit) */
33 #define AD7192_REG_STAT 0 /* Status Register (RO, 8-bit) */
34 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
35 #define AD7192_REG_CONF 2 /* Configuration Register (RW, 24-bit) */
36 #define AD7192_REG_DATA 3 /* Data Register (RO, 24/32-bit) */
37 #define AD7192_REG_ID 4 /* ID Register (RO, 8-bit) */
38 #define AD7192_REG_GPOCON 5 /* GPOCON Register (RO, 8-bit) */
39 #define AD7192_REG_OFFSET 6 /* Offset Register (RW, 16-bit */
[all …]
/openbmc/linux/sound/pci/
H A Dcs4281.c1 // SPDX-License-Identifier: GPL-2.0-or-later
29 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
119 #define BA0_DMR_SIZE20 (1<<20) /* Sample is 20-bit */
123 #define BA0_DMR_SIZE8 (1<<16) /* Sample is 8-bit */
129 #define BA0_DMR_AUTO (1<<4) /* Auto-Initialize */
186 #define BA0_GPIOR 0x03e8 /* GPIO Pin Interface Register */
214 #define BA0_SLT12O 0x041c /* Slot 12 GPIO Output Register for AC-Link */
218 #define BA0_SERMC_ODSEN2 (1<<25) /* On-Demand Support Enable ASDIN2 */
219 #define BA0_SERMC_ODSEN1 (1<<24) /* On-Demand Support Enable ASDIN1 */
240 #define BA0_SLT12M 0x045c /* Slot 12 Monitor Register for Primary AC-Link */
[all …]
/openbmc/linux/Documentation/sound/
H A Dalsa-configuration.rst2 Advanced Linux Sound Architecture - Driver Configuration guide
38 ----------
47 limiting card index for auto-loading (1-8);
49 For auto-loading more than one card, specify this option
50 together with snd-card-X aliases.
63 Module snd-pcm-oss
64 ------------------
86 regarding opening the device. When this option is non-zero,
90 Module snd-rawmidi
91 ------------------
[all …]
/openbmc/linux/drivers/iio/imu/bno055/
H A Dbno055.c1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2021-2022 Istituto Italiano di Tecnologia
23 #include <linux/gpio/consumer.h>
37 #define BNO055_FW_UID_FMT "bno055-caldata-%*phN.dat"
38 #define BNO055_FW_GENERIC_NAME "bno055-caldata.dat"
67 #define BNO055_SCAN_CH_COUNT ((BNO055_GRAVITY_DATA_Z_LSB_REG - BNO055_ACC_DATA_X_LSB_REG) / 2)
159 …* [0] https://community.bosch-sensortec.com/t5/MEMS-sensors-forum/BNO055-Wrong-sensitivity-resolu…
166 * where k is rad-to-deg factor
253 * Unreadable registers are indeed reserved; there are no WO regs in bno055_regmap_writeable()
301 dev_dbg(priv->dev, "Invalid calibration file size %d (expected %d)", in bno055_calibration_load()
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/openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_reg.h3 * Copyright (c) 2007-2013 Broadcom Corporation
13 * R - Read only
14 * RC - Clear on read
15 * RW - Read/Write
16 * ST - Statistics register (clear on read)
17 * W - Write only
18 * WB - Wide bus register - the size is over 32 bits and it should be
20 * WR - Write Clear (write 1 to clear the bit)
32 /* [RW 1] Initiate the ATC array - reset all the valid bits */
56 * BRB1_IND_FREE_LIST_PRS_CRDT+2 initialize parser initial credit. Warning -
[all …]

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