Home
last modified time | relevance | path

Searched +full:force +full:- +full:external +full:- +full:phy (Results 1 – 25 of 183) sorted by relevance

12345678

/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dsmsc,lan9115.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Smart Mixed-Signal Connectivity (SMSC) LAN911x/912x Controller
10 - Shawn Guo <shawnguo@kernel.org>
13 - $ref: ethernet-controller.yaml#
18 - const: smsc,lan9115
19 - items:
20 - enum:
21 - smsc,lan89218
[all …]
/openbmc/linux/Documentation/networking/device_drivers/ethernet/davicom/
H A Ddm9000.rst1 .. SPDX-License-Identifier: GPL-2.0
9 Ben Dooks <ben@simtec.co.uk> <ben-linux@fluff.org>
13 ------------
15 This file describes how to use the DM9000 platform-device based network driver
25 ----------------------------
37 An example from arch/arm/mach-s3c/mach-bast.c is::
91 -------------
94 device, whether or not an external PHY is attached to the device and
95 the availability of an external configuration EEPROM.
113 The chip is connected to an external PHY.
[all …]
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dphy-miphy28lp.txt1 STMicroelectronics STi MIPHY28LP PHY binding
4 This binding describes a miphy device that is used to control PHY hardware
8 - compatible : Should be "st,miphy28lp-phy".
9 - st,syscfg : Should be a phandle of the system configuration register group
12 Required nodes : A sub-node is required for each channel the controller
14 'reg' and 'reg-names' properties are used inside these
19 - #phy-cells : Should be 1 (See second example)
21 - PHY_TYPE_SATA
22 - PHY_TYPE_PCI
23 - PHY_TYPE_USB3
[all …]
/openbmc/linux/drivers/net/ethernet/davicom/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
31 bool "Force simple NSR based PHY polling"
36 costly MII PHY reads. Note, this will not work if the chip is
37 operating with an external PHY.
/openbmc/linux/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_x550.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
17 struct ixgbe_mac_info *mac = &hw->mac; in ixgbe_get_invariants_X550_x()
18 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_get_invariants_X550_x() local
19 struct ixgbe_link_info *link = &hw->link; in ixgbe_get_invariants_X550_x()
24 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) in ixgbe_get_invariants_X550_x()
25 phy->ops.set_phy_power = NULL; in ixgbe_get_invariants_X550_x()
27 link->addr = IXGBE_CS4227; in ixgbe_get_invariants_X550_x()
34 struct ixgbe_phy_info *phy = &hw->phy; in ixgbe_get_invariants_X550_x_fw() local
39 phy->ops.set_phy_power = NULL; in ixgbe_get_invariants_X550_x_fw()
[all …]
/openbmc/linux/arch/mips/include/asm/mach-bcm63xx/
H A Dbcm63xx_dev_enet.h1 /* SPDX-License-Identifier: GPL-2.0 */
21 /* or fill phy info to use an external one */
26 /* if has_phy, use autonegotiated pause parameters or force
68 #define ENETSW_PORTS_6328 5 /* 4 FE PHY + 1 RGMII */
69 #define ENETSW_PORTS_6368 6 /* 4 FE PHY + 2 RGMII */
/openbmc/linux/drivers/ata/
H A Dahci.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * ahci.h - Common AHCI SATA definitions and declarations
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2004-2005 Red Hat, Inc.
12 * as Documentation/driver-api/libata.rst
25 #include <linux/phy/phy.h>
80 HOST_RESET = BIT(0), /* reset controller; self-clear */
86 HOST_CAP_SXS = BIT(5), /* Supports External SATA */
92 HOST_CAP_FBS = BIT(16), /* FIS-based switching support */
98 HOST_CAP_SSS = BIT(27), /* Staggered Spin-up */
[all …]
/openbmc/linux/drivers/net/ethernet/sun/
H A Dsunhme.h1 /* SPDX-License-Identifier: GPL-2.0 */
38 #define GREG_STAT_ACNTEXP 0x00000004 /* Align-error counter expired */
39 #define GREG_STAT_CCNTEXP 0x00000008 /* CRC-error counter expired */
40 #define GREG_STAT_LCNTEXP 0x00000010 /* Length-error counter expired */
42 #define GREG_STAT_CVCNTEXP 0x00000040 /* Code-violation counter expired */
46 #define GREG_STAT_MAXPKTERR 0x00000400 /* Max-packet size error */
47 #define GREG_STAT_NCNTEXP 0x00000800 /* Normal-collision counter expired */
48 #define GREG_STAT_ECNTEXP 0x00001000 /* Excess-collision counter expired */
49 #define GREG_STAT_LCCNTEXP 0x00002000 /* Late-collision counter expired */
50 #define GREG_STAT_FCNTEXP 0x00004000 /* First-collision counter expired */
[all …]
H A Dsunhme.c1 // SPDX-License-Identifier: GPL-2.0
10 * 2000/11/11 Willy Tarreau <willy AT meta-x.org>
11 * - port to non-sparc architectures. Tested only on x86 and
13 * - ability to specify the MAC address at module load time by passing this
20 #include <linux/dma-mapping.h>
83 /* "Auto Switch Debug" aka phy debug */
111 tlp->tstamp = (unsigned int)jiffies;
112 tlp->tx_new = hp->tx_new;
113 tlp->tx_old = hp->tx_old;
114 tlp->action = a;
[all …]
/openbmc/u-boot/cmd/aspeed/nettest/
H A Dphy.c1 // SPDX-License-Identifier: GPL-2.0+
27 #include "phy.h"
63 //------------------------------------------------------------
64 // PHY R/W basic
65 //------------------------------------------------------------
71 if (eng->env.is_new_mdio_reg[eng->run.mdio_idx]) { in phy_write()
73 MDIO_SET_PHY_ADDR(eng->phy.Adr) | in phy_write()
75 writel(wr_data, eng->run.mdio_base); in phy_write()
76 /* check time-out */ in phy_write()
77 while (readl(eng->run.mdio_base) & MDIO_FIRE_BUSY) { in phy_write()
[all …]
/openbmc/linux/drivers/net/dsa/realtek/
H A Drtl8365mb.c1 // SPDX-License-Identifier: GPL-2.0
2 /* Realtek SMI subdriver for the Realtek RTL8365MB-VC ethernet switch.
4 * Copyright (C) 2021 Alvin Šipraga <alsi@bang-olufsen.dk>
5 * Copyright (C) 2021 Michael Rasmussen <mir@bang-olufsen.dk>
7 * The RTL8365MB-VC is a 4+1 port 10/100/1000M switch controller. It includes 4
9 * can be connected to the CPU - or another PHY - via either MII, RMII, or
15 * .-----------------------------------.
17 * UTP <---------------> Giga PHY <-> PCS <-> P0 GMAC |
18 * UTP <---------------> Giga PHY <-> PCS <-> P1 GMAC |
19 * UTP <---------------> Giga PHY <-> PCS <-> P2 GMAC |
[all …]
/openbmc/linux/drivers/net/ethernet/intel/igb/
H A De1000_defines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
62 /* Interrupt acknowledge Auto-mask */
118 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
119 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
123 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
184 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
185 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
186 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
188 #define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
[all …]
/openbmc/bmcweb/redfish-core/schema/dmtf/csdl/
H A DPortMetrics_v1.xml1 <?xml version="1.0" encoding="UTF-8"?>
2 <!---->
3 <!--################################################################################ -->
4 <!--# Redfish Schema: PortMetrics v1.7.0 -->
5 <!--# -->
6 <!--# For a detailed change log, see the README file contained in the DSP8010 bundle, -->
7 <!--# available at http://www.dmtf.org/standards/redfish -->
8 <!--# Copyright 2014-2024 DMTF. -->
9 <!--# For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright -->
10 <!--################################################################################ -->
[all …]
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dexynos-srom.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/exynos-srom.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 The SROM controller can be used to attach external peripherals. In this case
19 - const: samsung,exynos4210-srom
24 "#address-cells":
27 "#size-cells":
35 <bank-number> 0 <parent address of bank> <size>
[all …]
/openbmc/linux/drivers/net/dsa/mv88e6xxx/
H A Dglobal2.c1 // SPDX-License-Identifier: GPL-2.0-or-later
7 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
21 return mv88e6xxx_read(chip, chip->info->global2_addr, reg, val); in mv88e6xxx_g2_read()
26 return mv88e6xxx_write(chip, chip->info->global2_addr, reg, val); in mv88e6xxx_g2_write()
32 return mv88e6xxx_wait_bit(chip, chip->info->global2_addr, reg, in mv88e6xxx_g2_wait_bit()
146 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1; in mv88e6xxx_g2_trunk_mapping_write()
155 const u16 port_mask = BIT(mv88e6xxx_num_ports(chip)) - 1; in mv88e6xxx_g2_trunk_clear()
212 /* Offset 0x0B: Cross-chip Port VLAN (Addr) Register
213 * Offset 0x0C: Cross-chip Port VLAN Data Register
228 /* 9-bit Cross-chip PVT pointer: with MV88E6XXX_G2_MISC_5_BIT_PORT in mv88e6xxx_g2_pvt_op()
[all …]
/openbmc/linux/drivers/phy/
H A Dphy-xgene.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AppliedMicro X-Gene Multi-purpose PHY driver
10 * The APM X-Gene PHY consists of two PLL clock macro's (CMU) and lanes.
12 * PLL clock macro is used to generate the clock for the PHY. This driver
13 * configures the first PLL CMU, the second PLL CMU, and programs the PHY to
19 * -----------------
20 * | Internal | |------|
21 * | Ref PLL CMU |----| | ------------- ---------
22 * ------------ ---- | MUX |-----|PHY PLL CMU|----| Serdes|
23 * | | | | ---------
[all …]
/openbmc/linux/drivers/phy/allwinner/
H A Dphy-sun4i-usb.c1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * Allwinner sun4i USB phy driver
5 * Copyright (C) 2014-2015 Hans de Goede <hdegoede@redhat.com>
18 #include <linux/extcon-provider.h>
27 #include <linux/phy/phy.h>
28 #include <linux/phy/phy-sun4i-usb.h>
58 /* sunxi has the phy id/vbus pins not connected, so we use the force bits */
70 /* Private Control Bits for Each PHY */
120 struct phy *phy; member
145 #define to_sun4i_usb_phy_data(phy) \ argument
[all …]
/openbmc/linux/drivers/net/ethernet/broadcom/bnx2x/
H A Dbnx2x_link.c1 /* Copyright 2008-2013 Broadcom Corporation
8 * at http://www.gnu.org/licenses/gpl-2.0.html (the "GPL").
32 typedef int (*read_sfp_module_eeprom_func_p)(struct bnx2x_phy *phy,
43 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
205 (_phy)->def_md_devad, \
211 (_phy)->def_md_devad, \
217 static int bnx2x_sfp_module_detection(struct bnx2x_phy *phy,
239 * bnx2x_check_lfa - This function checks if link reinitialization is required,
251 struct bnx2x *bp = params->bp; in bnx2x_check_lfa()
254 REG_RD(bp, params->lfa_base + in bnx2x_check_lfa()
[all …]
/openbmc/qemu/pc-bios/
H A Dpetalogix-ml605.dts5 * SPDX-License-Identifier: GPL-2.0+
8 /dts-v1/;
11 #address-cells = < 0x01 >;
12 #size-cells = < 0x01 >;
22 ethernet0 = "/axi/axi-ethernet@82780000";
28 stdout-path = "/axi/serial@83e00000";
32 #address-cells = < 0x01 >;
34 #size-cells = < 0x00 >;
37 clock-frequency = < 0xbebc200 >;
38 compatible = "xlnx,microblaze-8.10.a";
[all …]
/openbmc/linux/drivers/net/ethernet/intel/e1000e/
H A Ddefines.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
17 #define E1000_WUC_PHY_WAKE 0x00000100 /* if PHY supports wakeup */
37 #define E1000_CTRL_EXT_FORCE_SMBUS 0x00000800 /* Force SMBus mode */
46 #define E1000_CTRL_EXT_IAME 0x08000000 /* Int ACK Auto-mask */
100 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
101 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
104 #define E1000_MANC_BLK_PHY_RST_ON_IDE 0x00040000 /* Block phy resets */
183 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
184 #define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
[all …]
/openbmc/linux/arch/arm/boot/dts/st/
H A Dstm32mp157c-lxa-mc1.dts1 /* SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) */
3 * Copyright (C) 2020 STMicroelectronics - All Rights Reserved
7 /dts-v1/;
10 #include "stm32mp15xx-osd32.dtsi"
11 #include "stm32mp15xxac-pinctrl.dtsi"
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/pwm/pwm.h>
17 model = "Linux Automation MC-1 board";
18 compatible = "lxa,stm32mp157c-mc1", "oct,stm32mp15xx-osd32", "st,stm32mp157";
28 compatible = "pwm-backlight";
[all …]
/openbmc/linux/drivers/usb/dwc2/
H A Dcore.c1 // SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
3 * core.c - DesignWare HS OTG Controller common routines
5 * Copyright (C) 2004-2013 Synopsys, Inc.
18 #include <linux/dma-mapping.h>
31 * dwc2_backup_global_registers() - Backup global controller registers.
41 dev_dbg(hsotg->dev, "%s\n", __func__); in dwc2_backup_global_registers()
44 gr = &hsotg->gr_backup; in dwc2_backup_global_registers()
46 gr->gotgctl = dwc2_readl(hsotg, GOTGCTL); in dwc2_backup_global_registers()
47 gr->gintmsk = dwc2_readl(hsotg, GINTMSK); in dwc2_backup_global_registers()
48 gr->gahbcfg = dwc2_readl(hsotg, GAHBCFG); in dwc2_backup_global_registers()
[all …]
/openbmc/linux/drivers/net/fddi/skfp/
H A Dpcmplc.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 * The following external SMT functions are referenced :
26 * The following external HW dependent functions are referenced :
67 #define GO_STATE(x) (mib->fddiPORTPCMState = (x)|AFLAG)
68 #define ACTIONS_DONE() (mib->fddiPORTPCMState &= ~AFLAG)
109 * PCL-S control register
110 * this register in the PLC-S controls the scrambling parameters
121 * PCL-S control register
122 * this register in the PLC-S controls the scrambling parameters
133 * external vars
[all …]
/openbmc/linux/drivers/net/ethernet/smsc/
H A Dsmsc911x.c1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2004-2008 SMSC
5 * Copyright (C) 2005-2008 ARM
42 #include <linux/phy.h>
56 #define SMSC_MDIONAME "smsc911x-mdio"
57 #define SMSC_DRV_VERSION "2008-10-21"
145 #define __smsc_shift(pdata, reg) ((reg) << ((pdata)->config.shift))
149 if (pdata->config.flags & SMSC911X_USE_32BIT) in __smsc911x_reg_read()
150 return readl(pdata->ioaddr + reg); in __smsc911x_reg_read()
152 if (pdata->config.flags & SMSC911X_USE_16BIT) in __smsc911x_reg_read()
[all …]
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_dfs.c1 // SPDX-License-Identifier: GPL-2.0
72 /* Poll - Wait for Refresh operation completion */ in wait_refresh_op_complete()
82 * Args: target_freq - target frequency
84 * Returns: freq_par - the ratio parameter
95 /* Find the ratio between PLL frequency and ddr-clk */ in ddr3_get_freq_parameter()
108 * Args: freq - target frequency
110 * Returns: MV_OK - success, MV_FAIL - fail
119 DEBUG_DFS_C("DDR3 - DFS - High To Low - Starting DFS procedure to Frequency - ", in ddr3_dfs_high_2_low()
122 /* target frequency - 100MHz */ in ddr3_dfs_high_2_low()
131 /* Configure - DRAM DLL final state after DFS is complete - Enable */ in ddr3_dfs_high_2_low()
[all …]

12345678