| /openbmc/linux/Documentation/devicetree/bindings/edac/ |
| H A D | socfpga-eccmgr.txt | 1 Altera SoCFPGA ECC Manager
2 This driver uses the EDAC framework to implement the SOCFPGA ECC Manager.
3 The ECC Manager counts and corrects single bit errors and counts/handles
6 Cyclone5 and Arria5 ECC Manager
8 - compatible : Should be "altr,socfpga-ecc-manager"
9 - #address-cells: must be 1
10 - #size-cells: must be 1
11 - ranges : standard definition, should translate from local addresses
15 L2 Cache ECC
17 - compatible : Should be "altr,socfpga-l2-ecc"
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| /openbmc/linux/Documentation/devicetree/bindings/mtd/ |
| H A D | hisi504-nand.txt | 5 - compatible: Should be "hisilicon,504-nfc".
6 - reg: The first contains base physical address and size of
8 physical address and size of NAND controller's buffer.
9 - interrupts: Interrupt number for nfc.
10 - nand-bus-width: See nand-controller.yaml.
11 - nand-ecc-mode: Support none and hw ecc mode.
12 - #address-cells: Partition address, should be set 1.
13 - #size-cells: Partition size, should be set 1.
17 - nand-ecc-strength: Number of bits to correct per ECC step.
18 - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
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| H A D | mediatek,mtk-nfc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/mediatek,mtk-nfc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Xiangsheng Hou <xiangsheng.hou@mediatek.com>
15 - mediatek,mt2701-nfc
16 - mediatek,mt2712-nfc
17 - mediatek,mt7622-nfc
21 - description: Base physical address and size of NFI.
25 - description: NFI interrupt
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| H A D | atmel-nand.txt | 4 Documentation/devicetree/bindings/memory-controllers/atmel,ebi.txt).
6 The NAND controller might be connected to an ECC engine.
11 - compatible: should be one of the following
12 "atmel,at91rm9200-nand-controller"
13 "atmel,at91sam9260-nand-controller"
14 "atmel,at91sam9261-nand-controller"
15 "atmel,at91sam9g45-nand-controller"
16 "atmel,sama5d3-nand-controller"
17 "microchip,sam9x60-nand-controller"
18 - ranges: empty ranges property to forward EBI ranges definitions.
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| H A D | vf610-nfc.txt | 7 - compatible: Should be set to "fsl,vf610-nfc".
8 - reg: address range of the NFC.
9 - interrupts: interrupt of the NFC.
10 - #address-cells: shall be set to 1. Encode the nand CS.
11 - #size-cells : shall be set to 0.
12 - assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>;
13 - assigned-clock-rates: The NAND bus timing is derived from this clock
17 there might be restrictions on maximum rates when using hardware ECC.
19 - #address-cells, #size-cells : Must be present if the device has sub-nodes
27 - compatible: Should be set to "fsl,vf610-nfc-cs".
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| H A D | rockchip,nand-controller.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/rockchip,nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - $ref: nand-controller.yaml#
13 - Heiko Stuebner <heiko@sntech.de>
18 - const: rockchip,px30-nfc
19 - const: rockchip,rk2928-nfc
20 - const: rockchip,rv1108-nfc
21 - items:
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| H A D | denali,nand.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
15 - altr,socfpga-denali-nand
16 - socionext,uniphier-denali-nand-v5a
17 - socionext,uniphier-denali-nand-v5b
19 reg-names:
25 - const: nand_data
26 - const: denali_reg
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| H A D | raw-nand-chip.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mtd/raw-nand-chip.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Miquel Raynal <miquel.raynal@bootlin.com>
13 - $ref: nand-chip.yaml#
16 The ECC strength and ECC step size properties define the user
18 they request the ECC engine to correct {strength} bit errors per
19 {size} bytes for a particular raw NAND chip.
21 The interpretation of these parameters is implementation-defined, so
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| /openbmc/u-boot/doc/ |
| H A D | README.nand | 1 # SPDX-License-Identifier: GPL-2.0+
21 nand erase off|partition size
22 nand erase clean [off|partition size]
23 Erase `size' bytes starting at offset `off'. Alternatively partition
24 name can be specified, in this case size will be eventually limited
25 to not exceed partition size (this behaviour applies also to read
28 If `erase' is specified without an offset or size, the entire flash
30 size, the entire partition is erased.
32 If `clean' is specified, a JFFS2-style clean marker is written to
43 nand read addr ofs|partition size
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| /openbmc/u-boot/board/ge/common/ |
| H A D | vpd_reader.c | 1 // SPDX-License-Identifier: GPL-2.0+
37 ((((1 << gfo) - 1) - ((int)source_length * 8)) < 0); in calculate_galois_field_order()
42 return -1; in calculate_galois_field_order()
48 size_t data_length, const u8 *ecc, size_t ecc_length) in verify_bch() argument
53 return -1; in verify_bch()
58 return -1; in verify_bch()
60 if (bch->ecc_bytes != ecc_length) { in verify_bch()
62 return -1; in verify_bch()
67 int errors = decode_bch(bch, data, data_length, ecc, NULL, NULL, in verify_bch()
73 return -1; in verify_bch()
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| /openbmc/u-boot/drivers/mtd/nand/raw/ |
| H A D | Kconfig | 9 This option, if enabled, provides more flexible and linux-like
15 Omit standard ECC layouts to safe space. Select this if your driver
16 is known to provide its own ECC layout.
28 bool "Atmel Hardware ECC"
32 bool "Atmel Programmable Multibit ECC (PMECC)"
36 The Programmable Multibit ECC (PMECC) controller is a programmable
40 int "PMECC Correctable ECC Bits"
44 Correctable ECC bits, can be 2, 4, 8, 12, and 24.
47 int "PMECC Sector Size"
51 Sector size, in bytes, can be 512 or 1024.
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| H A D | sunxi_nand.c | 1 // SPDX-License-Identifier: GPL-2.0+
7 * https://github.com/yuq/sunxi-nfc-mtd
10 * https://github.com/hno/Allwinner-Info
78 #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
114 #define NFC_ADR_NUM(x) (((x) - 1) << 16)
212 * sunxi HW ECC infos: stores information related to HW ECC support
214 * @mode: the sunxi ECC mode field deduced from ECC requirements
215 * @layout: the OOB layout depending on the ECC requirements and the
216 * selected ECC mode
292 div_m = (clock_get_pll6() + hz - 1) / hz; in sunxi_nfc_set_clk_rate()
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| H A D | nand_base.c | 7 * http://www.linux-mtd.infradead.org/doc/nand.html
10 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
16 * rework for 2K page size chips
19 * Enable cached programming for 2k page size chips
20 * Check, if mtd->ecctype should be set to MTD_ECC_HW
21 * if we have HW ECC support.
113 if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) { in check_offs_len()
115 ret = -EINVAL; in check_offs_len()
119 if (len & ((1ULL << chip->phys_erase_shift) - 1)) { in check_offs_len()
121 ret = -EINVAL; in check_offs_len()
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| H A D | denali.c | 1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2013-2014, Altera Corporation <www.altera.com>
5 * Copyright (C) 2009-2010, Intel Corporation and its suppliers.
11 #include <linux/dma-direction.h>
19 static dma_addr_t dma_map_single(void *dev, void *ptr, size_t size, in dma_map_single() argument
24 size = ALIGN(size, ARCH_DMA_MINALIGN); in dma_map_single()
27 invalidate_dcache_range(addr, addr + size); in dma_map_single()
29 flush_dcache_range(addr, addr + size); in dma_map_single()
34 static void dma_unmap_single(void *dev, dma_addr_t addr, size_t size, in dma_unmap_single() argument
37 size = ALIGN(size, ARCH_DMA_MINALIGN); in dma_unmap_single()
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| H A D | atmel_nand.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2007-2008
9 * Add Programmable Multibit ECC support for various AT91 SoC
30 #include "atmel_nand_ecc.h" /* Hardware ECC registers */
71 * Return number of ecc bytes per sector according to sector size and
77 * 2-bits 4-bytes 4-bytes
78 * 4-bits 7-bytes 7-bytes
79 * 8-bits 13-bytes 14-bytes
80 * 12-bits 20-bytes 21-bytes
81 * 24-bits 39-bytes 42-bytes
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| H A D | mxc_nand.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2004-2007 Freescale Semiconductor, Inc.
14 #include <asm/arch/imx-regs.h>
40 /* Macros to get byte and bit positions of ECC */
48 /* OOB placement block for use with hardware ecc generation */
98 static uint32_t *mxc_nand_memcpy32(uint32_t *dest, uint32_t *source, size_t size) in mxc_nand_memcpy32() argument
102 size >>= 2; in mxc_nand_memcpy32()
103 while (size--) in mxc_nand_memcpy32()
117 while (max_retries-- > 0) {
119 tmp = readnfc(&host->regs->config2);
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| H A D | lpc32xx_nand_slc.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2015-2018 Vladimir Zapolskiy <vz@mleia.com>
8 * Hardware ECC support original source code
38 u32 ecc; member
44 #define CFG_DMA_ECC (1 << 4) /* Enable DMA ECC bit */
45 #define CFG_ECC_EN (1 << 3) /* ECC enable bit */
51 #define CTRL_ECC_CLEAR (1 << 1) /* Reset ECC bit */
72 /* NAND ECC Layout for small page NAND devices
88 * For Large Block: 17 descriptors = ((16 Data and ECC Read) + 1 Spare Area)
89 * For Small Block: 5 descriptors = ((4 Data and ECC Read) + 1 Spare Area)
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| H A D | nand_bch.c | 1 // SPDX-License-Identifier: GPL-2.0+
3 * This file provides ECC correction for more than 1 bit per block of data,
22 * struct nand_bch_control - private NAND BCH control structure
24 * @ecclayout: private ecc layout for this BCH configuration
26 * @eccmask: XOR ecc mask, allows erased pages to be decoded as valid
36 * nand_bch_calculate_ecc - [NAND Interface] Calculate ECC for data block
39 * @code: output buffer with ECC
45 struct nand_bch_control *nbc = chip->ecc.priv; in nand_bch_calculate_ecc()
48 memset(code, 0, chip->ecc.bytes); in nand_bch_calculate_ecc()
49 encode_bch(nbc->bch, buf, chip->ecc.size, code); in nand_bch_calculate_ecc()
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| /openbmc/linux/drivers/edac/ |
| H A D | ppc4xx_edac.c | 1 // SPDX-License-Identifier: GPL-2.0-only
25 * associated with the IMB DDR2 ECC controller found in the AMCC/IBM
30 * - Support for registered- and non-registered DDR1 and DDR2 memory.
31 * - 32-bit or 16-bit memory interface with optional ECC.
33 * o ECC support includes:
35 * - 4-bit SEC/DED
36 * - Aligned-nibble error detect
37 * - Bypass mode
39 * - Two (2) memory banks/ranks.
40 * - Up to 1 GiB per bank/rank in 32-bit mode and up to 512 MiB per
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| /openbmc/linux/drivers/mtd/nand/raw/ |
| H A D | sunxi_nand.c | 1 // SPDX-License-Identifier: GPL-2.0+
6 * https://github.com/yuq/sunxi-nfc-mtd
9 * https://github.com/hno/Allwinner-Info
16 #include <linux/dma-mapping.h>
70 #define NFC_PAGE_SHIFT(x) (((x) < 10 ? 0 : (x) - 10) << 8)
107 #define NFC_ADR_NUM(x) (((x) - 1) << 16)
161 * struct sunxi_nand_chip_sel - stores information related to NAND Chip Select
164 * @rb: the Ready/Busy pin ID. -1 means no R/B pin connected to the NFC
172 * struct sunxi_nand_hw_ecc - stores information related to HW ECC support
181 * struct sunxi_nand_chip - stores NAND chip device related information
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| H A D | mtk_nand.c | 1 // SPDX-License-Identifier: GPL-2.0 OR MIT
6 * Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
10 #include <linux/dma-mapping.h>
19 #include <linux/mtd/nand-ecc-mtk.h>
89 #define MTK_NAME "mtk-nand"
146 struct mtk_ecc *ecc; member
161 * supported spare size of each IP.
162 * order should be the same with the spare size bitfiled defination of
185 return (u8 *)p + i * chip->ecc.size; in data_ptr()
197 if (i < mtk_nand->bad_mark.sec) in oob_ptr()
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| H A D | nand_base.c | 1 // SPDX-License-Identifier: GPL-2.0-only
8 * http://www.linux-mtd.infradead.org/doc/nand.html
11 * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
17 * rework for 2K page size chips
20 * Enable cached programming for 2k page size chips
21 * Check, if mtd->ecctype should be set to MTD_ECC_HW
22 * if we have HW ECC support.
38 #include <linux/mtd/nand-ecc-sw-hamming.h>
39 #include <linux/mtd/nand-ecc-sw-bch.h>
53 int lastpage = (mtd->erasesize / mtd->writesize) - 1; in nand_pairing_dist3_get_info()
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| H A D | qcom_nandc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include <linux/dma-mapping.h>
172 * the NAND controller performs reads/writes with ECC in 516 byte chunks.
178 * the largest page size we support is 8K, this will have 16 steps/codewords
186 /* ECC modes supported by the controller */
207 #define dev_cmd_reg_addr(nandc, reg) ((nandc)->props->dev_cmd_reg_start + (reg))
210 #define nandc_reg_phys(chip, offset) ((chip)->base_phys + (offset))
214 ((chip)->reg_read_dma + \
215 ((u8 *)(vaddr) - (u8 *)(chip)->reg_read_buf))
244 * @bam_ce - the array of BAM command elements
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| /openbmc/linux/drivers/mtd/nand/raw/ingenic/ |
| H A D | ingenic_nand_drv.c | 1 // SPDX-License-Identifier: GPL-2.0
23 #include <linux/jz4780-nemc.h>
27 #define DRV_NAME "ingenic-nand"
44 struct ingenic_ecc *ecc; member
75 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_ecc() local
77 if (section || !ecc->total) in qi_lb60_ooblayout_ecc()
78 return -ERANGE; in qi_lb60_ooblayout_ecc()
80 oobregion->length = ecc->total; in qi_lb60_ooblayout_ecc()
81 oobregion->offset = 12; in qi_lb60_ooblayout_ecc()
90 struct nand_ecc_ctrl *ecc = &chip->ecc; in qi_lb60_ooblayout_free() local
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| /openbmc/u-boot/include/linux/mtd/ |
| H A D | rawnand.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright © 2000-2010 David Woodhouse <dwmw2@infradead.org>
39 * and override command or ECC setup according to flash type.
104 /* Extended commands for AG-AND device */
115 /* multi-bank error status (banks 0-3) */
123 #define NAND_CMD_NONE -1
132 #define NAND_DATA_IFACE_CHECK_ONLY -1
153 * Constants for Hardware ECC
155 /* Reset Hardware ECC for read */
157 /* Reset Hardware ECC for write */
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