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/openbmc/u-boot/board/micronas/vct/
H A Dscc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
11 #define DMA_READ 0 /* SCC read DMA */
12 #define DMA_WRITE 1 /* SCC write DMA */
14 #define DMA_LINEAR 0 /* DMA linear buffer access method */
15 #define DMA_CYCLIC 1 /* DMA cyclic buffer access method */
17 #define DMA_START 0 /* DMA command - start DMA */
18 #define DMA_STOP 1 /* DMA command - stop DMA */
19 #define DMA_START_FH_RESET 2 /* DMA command - start DMA reset FH */
20 #define DMA_TAKEOVER 15 /* DMA command - commit the DMA conf */
25 #define USE_NO_FH 0 /* order the DMA to not use FH */
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/openbmc/qemu/scripts/oss-fuzz/
H A Dreorder_fuzzer_qtest_trace.py2 # -*- coding: utf-8 -*-
6 trace that you can feed into a standard qemu-system process. Example usage:
8 QEMU_FUZZ_ARGS="-machine q35,accel=qtest" QEMU_FUZZ_OBJECTS="*" \
9 ./i386-softmmu/qemu-fuzz-i386 --fuzz-target=generic-pci-fuzz
12 QEMU_FUZZ_ARGS="-machine q35,accel=qtest" QEMU_FUZZ_OBJECTS="*" \
13 ./i386-softmmu/qemu-fuzz-i386 --fuzz-target=generic-pci-fuzz
15 scripts/oss-fuzz/reorder_fuzzer_qtest_trace.py qtest_log_output > qtest_trace
16 ./i386-softmmu/qemu-fuzz-i386 -machine q35,accel=qtest \
17 -qtest stdio < qtest_trace
22 before a DMA read from that range. This means that the fuzzer can produce
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/openbmc/linux/drivers/scsi/
H A Dzorro_esp.c1 // SPDX-License-Identifier: GPL-2.0
3 * ESP front-end for Amiga ZORRO SCSI systems.
11 * Blizzard 1230 DMA and probe function fixes
24 * Rewritten to use 53c700.c by Kars de Jong <jongk@linux-m68k.org>
32 #include <linux/dma-mapping.h>
55 /* per-board register layout definitions */
57 /* Blizzard 1230 DMA interface */
60 unsigned char dma_addr; /* DMA address [0x0000] */
62 unsigned char dma_latch; /* DMA latch [0x8000] */
65 /* Blizzard 1230II DMA interface */
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/openbmc/u-boot/include/
H A DSA-1100.h2 * FILE SA-1100.h
8 * System StrongARM SA-1100
11 * SA-1100 microprocessor (Advanced RISC Machine (ARM)
13 * StrongARM SA-1100 data sheet version 2.2.
15 * Language-specific definitions are selected by the
33 #include <asm/arch-sa1100/bitfield.h>
185 * Controller (UDC) Control Register (read/write).
187 * Controller (UDC) Address Register (read/write).
190 * (read/write).
193 * (read/write).
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/openbmc/linux/Documentation/devicetree/bindings/dma/
H A Dqcom_hidma_mgmt.txt3 Qualcomm Technologies HIDMA is a high speed DMA device. It only supports
7 Each HIDMA HW instance consists of multiple DMA channels. These channels
14 instance can use like maximum read/write request and number of bytes to
15 read/write in a single burst.
18 - compatible: "qcom,hidma-mgmt-1.0";
19 - reg: Address range for DMA device
20 - dma-channels: Number of channels supported by this DMA controller.
21 - max-write-burst-bytes: Maximum write burst in bytes that HIDMA can
26 - max-read-burst-bytes: Maximum read burst in bytes that HIDMA can
31 - max-write-transactions: This value is how many times a write burst is
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H A Dk3dma.txt1 * Hisilicon K3 DMA controller
3 See dma.txt first
6 - compatible: Must be one of
7 - "hisilicon,k3-dma-1.0"
8 - "hisilicon,hisi-pcm-asp-dma-1.0"
9 - reg: Should contain DMA registers location and length.
10 - interrupts: Should contain one interrupt shared by all channel
11 - #dma-cells: see dma.txt, should be 1, para number
12 - dma-channels: physical channels supported
13 - dma-requests: virtual channels supported, each virtual channel
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H A Dintel,ldma.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/dma/intel,ldma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lightning Mountain centralized DMA controllers.
10 - chuanhua.lei@intel.com
11 - mallikarjunax.reddy@intel.com
14 - $ref: dma-controller.yaml#
19 - intel,lgm-cdma
20 - intel,lgm-dma2tx
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H A Drenesas,nbpfaxi.txt1 * Renesas "Type-AXI" NBPFAXI* DMA controllers
3 * DMA controller
7 - compatible: must be one of
17 - #dma-cells: must be 2: the first integer is a terminal number, to which this
26 - max-burst-mem-read: limit burst size for memory reads
29 - max-burst-mem-write: limit burst size for memory writes
32 If both max-burst-mem-read and max-burst-mem-write are set, DMA_MEM_TO_MEM
35 You can use dma-channels and dma-requests as described in dma.txt, although they
40 dma: dma-controller@48000000 {
51 #dma-cells = <2>;
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/openbmc/linux/drivers/staging/rtl8723bs/include/
H A Drtl8723b_spec.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
10 #define HAL_NAV_UPPER_UNIT_8723B 128 /* micro-second */
59 #define REG_RXDMA_CONTROL_8723B 0x0286 /* Control the RX DMA. */
77 #define REG_DBI_WDATA_8723B 0x0348 /* DBI Write Data */
80 #define REG_DBI_FLAG_8723B 0x0352 /* DBI Read/Write Flag */
81 #define REG_MDIO_WDATA_8723B 0x0354 /* MDIO for Write PCIE PHY */
87 #define REG_PCIE_MULTIFET_CTRL_8723B 0x036A /* PCIE Multi-Fethc Control */
190 /* IMR DW0(0x00B0-00B3) Bit 0-31 */
199 #define IMR_BCNDMAINT0_8723B BIT20 /* Beacon DMA Interrupt 0 */
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/openbmc/linux/include/uapi/linux/
H A Ddma-buf.h1 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
26 * struct dma_buf_sync - Synchronize with CPU access.
28 * When a DMA buffer is accessed from the CPU via mmap, it is not always
29 * possible to guarantee coherency between the CPU-visible map and underlying
35 * with DMA_BUF_SYNC_START and the appropriate read/write flags. Once the
37 * DMA_BUF_SYNC_END and the same read/write flags.
45 * follow-up work is not submitted to GPU or other device driver until
50 * poll() on the DMA buffer file descriptor. If the driver or API requires
52 * other synchronization primitive outside the scope of the DMA buffer API.
65 * Indicates that the mapped DMA buffer will be read by the
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/openbmc/u-boot/arch/powerpc/include/asm/
H A Dfsl_dma.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Freescale DMA Controller
15 uint mr; /* DMA mode register */
20 #define FSL_DMA_MR_EOTIE 0x00000080 /* End-of-transfer interrupt en */
30 #define FSL_DMA_MR_DRCNT 0x0f000000 /* DMA request count */
31 uint sr; /* DMA status register */
32 #define FSL_DMA_SR_EOCDI 0x00000001 /* End-of-chain/direct interrupt */
33 #define FSL_DMA_SR_EOSI 0x00000002 /* End-of-segment interrupt */
36 uint cdar; /* DMA current descriptor address register */
38 uint sar; /* DMA source address register */
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/openbmc/linux/Documentation/devicetree/bindings/gpu/host1x/
H A Dnvidia,tegra210-nvenc.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
15 - Thierry Reding <treding@gmail.com>
16 - Mikko Perttunen <mperttunen@nvidia.com>
20 pattern: "^nvenc@[0-9a-f]*$"
24 - nvidia,tegra210-nvenc
25 - nvidia,tegra186-nvenc
26 - nvidia,tegra194-nvenc
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/openbmc/linux/sound/mips/
H A Dhal2.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * Copyright (c) 2001, 2002, 2003 Ladislav Michl <ladis@linux-mips.org>
31 * Address of indirect internal register to be accessed. A write to this
32 * register initiates read or write access to the indirect registers in the
33 * HAL2. Note that there af four indirect data registers for write access to
39 /* 1=DMA Port */
40 /* 9=Global DMA Control */
46 /* If IAR_TYPE_M=DMA Port: */
53 /* If IAR_TYPE_M=Global DMA Control: */
61 #define H2_IAR_ACCESS_SELECT 0x0080 /* 1=read 0=write */
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/openbmc/linux/include/linux/dma/
H A Dedma.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
30 * struct dw_edma_core_ops - platform-specific eDMA methods
32 * method accepts the channel id in the end-to-end
33 * numbering with the eDMA write channels being placed
56 * enum dw_edma_chip_flags - Flags specific to an eDMA chip
64 * struct dw_edma_chip - representation of DesignWare eDMA controller hardware
67 * @nr_irqs: total number of DMA IRQs
68 * @ops DMA channel to IRQ number mapping
70 * @reg_base DMA register base address
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/openbmc/linux/drivers/mtd/nand/raw/
H A Dr852.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright © 2009 - Maxim Levitsky
15 byte write/read does one cycle on nand data lines.
16 dword write/read does 4 cycles
18 results of ecc correction, if DMA read was done before.
19 If write was done two dword reads read generated ecc checksums
26 #define R852_CTL_DATA 0x02 /* read/write data (#ALE)*/
30 #define R852_CTL_CARDENABLE 0x10 /* probably (#CE) - always set*/
32 #define R852_CTL_ECC_ACCESS 0x40 /* read/write ecc via reg #0*/
42 #define R852_CARD_STA_BUSY 0x80 /* card is busy - (#R/B) */
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/openbmc/qemu/hw/dma/
H A Dtrace-events5 jazzio_write(uint64_t addr, uint32_t val) "write reg[0x%"PRIx64"] = 0x%x"
7 rc4030_write(uint64_t addr, uint32_t val) "write reg[0x%"PRIx64"] = 0x%x"
10 ledma_memory_read(uint64_t addr, int len) "DMA read addr 0x%"PRIx64 " len %d"
11 ledma_memory_write(uint64_t addr, int len) "DMA write addr 0x%"PRIx64 " len %d"
14 espdma_memory_read(uint32_t addr, int len) "DMA read addr 0x%08x len %d"
15 espdma_memory_write(uint32_t addr, int len) "DMA write addr 0x%08x len %d"
17 …dma_mem_writel(uint64_t addr, uint32_t old, uint32_t val) "write dmareg 0x%"PRIx64": 0x%08x -> 0x%…
18 sparc32_dma_enable_raise(void) "Raise DMA enable"
19 sparc32_dma_enable_lower(void) "Lower DMA enable"
22 i8257_unregistered_dma(int nchan, int dma_pos, int dma_len) "unregistered DMA channel used nchan=%d…
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/openbmc/u-boot/drivers/spi/
H A Dmxs_spi.c1 // SPDX-License-Identifier: GPL-2.0+
8 * NOTE: This driver only supports the SPI-controller chipselects,
19 #include <asm/arch/imx-regs.h>
21 #include <asm/mach-imx/dma.h>
68 mxs_slave->max_khz = max_hz / 1000; in spi_setup_slave()
69 mxs_slave->mode = mode; in spi_setup_slave()
70 mxs_slave->regs = mxs_ssp_regs_by_bus(bus); in spi_setup_slave()
72 return &mxs_slave->slave; in spi_setup_slave()
88 struct mxs_ssp_regs *ssp_regs = mxs_slave->regs; in spi_claim_bus()
91 mxs_reset_block(&ssp_regs->hw_ssp_ctrl0_reg); in spi_claim_bus()
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/openbmc/linux/drivers/staging/rtl8723bs/hal/
H A DHal8723BReg.h1 /* SPDX-License-Identifier: GPL-2.0 */
149 #define REG_FW_UPD_RDPTR_8723B 0x0284 /* FW shall update this register before FW write RXPKT_REL…
150 #define REG_RXDMA_CONTROL_8723B 0x0286 /* Control the RX DMA. */
173 #define REG_DBI_WDATA_8723B 0x0348 /* DBI Write Data */
176 #define REG_DBI_FLAG_8723B 0x0352 /* DBI Read/Write Flag */
177 #define REG_MDIO_WDATA_8723B 0x0354 /* MDIO for Write PCIE PHY */
183 #define REG_PCIE_MULTIFET_CTRL_8723B 0x036A /* PCIE Multi-Fethc Control */
261 /* Format for offset 540h-542h: */
268 /* |<--Setup--|--Hold------------>| */
269 /* --------------|---------------------- */
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/openbmc/linux/drivers/i2c/busses/
H A Di2c-at91-master.c1 // SPDX-License-Identifier: GPL-2.0
3 * i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
18 #include <linux/dma-mapping.h>
30 #include "i2c-at91.h"
34 struct at91_twi_pdata *pdata = dev->pdata; in at91_init_twi_bus_master()
38 if (dev->fifo_size) in at91_init_twi_bus_master()
42 at91_twi_write(dev, AT91_TWI_CWGR, dev->twi_cwgr_reg); in at91_init_twi_bus_master()
45 if (pdata->has_dig_filtr && dev->enable_dig_filt) in at91_init_twi_bus_master()
49 if (pdata->has_adv_dig_filtr && dev->enable_dig_filt) in at91_init_twi_bus_master()
51 (AT91_TWI_FILTR_THRES(dev->filter_width) & in at91_init_twi_bus_master()
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/openbmc/linux/Documentation/PCI/
H A Dpci.rst1 .. SPDX-License-Identifier: GPL-2.0
4 How To Write Linux PCI Drivers
7 :Authors: - Martin Mares <mj@ucw.cz>
8 - Grant Grundler <grundler@parisc-linux.org>
11 Since each CPU architecture implements different chip-sets and PCI devices
18 by Jonathan Corbet, Alessandro Rubini, and Greg Kroah-Hartman.
26 "Linux PCI" <linux-pci@atrey.karlin.mff.cuni.cz> mailing list.
38 supporting hot-pluggable PCI, CardBus, and Express-Card in a single driver].
45 - Enable the device
46 - Request MMIO/IOP resources
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/openbmc/linux/Documentation/devicetree/bindings/firmware/
H A Dnvidia,tegra186-bpmp.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/nvidia,tegra186-bpmp.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
25 - .../mailbox/mailbox.txt
26 - .../mailbox/nvidia,tegra186-hsp.yaml
32 - .../clock/clock-bindings.txt
33 - <dt-bindings/clock/tegra186-clock.h>
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/openbmc/linux/drivers/comedi/drivers/
H A Dplx9080.h1 /* SPDX-License-Identifier: GPL-2.0+ */
26 * struct plx_dma_desc - DMA descriptor format for PLX PCI 9080
32 * Describes the format of a scatter-gather DMA descriptor for the PLX
33 * PCI 9080. All members are raw, little-endian register values that
34 * will be transferred by the DMA engine from local or PCI memory into
35 * corresponding registers for the DMA channel.
37 * The DMA descriptors must be aligned on a 16-byte boundary. Bits 3:0
82 /* DMA Arbitration Register (alias of MARBR). */
99 /* DMA Channel Priority */
101 #define PLX_MARBR_PRIO_DMA0 (BIT(19) * 1) /* DMA channel 0 has priority */
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/openbmc/linux/drivers/crypto/intel/keembay/
H A Docs-aes.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2018-2020 Intel Corporation
8 #include <linux/dma-mapping.h>
20 #include "ocs-aes.h"
76 * This bit activates the DMA. When the DMA finishes, it resets
81 * this bit is reset by the DMA.
84 * terminated this bit is reset by the DMA.
131 * 11-bit value, but it is actually 10-bits.
137 * before the tag is written. For 128-bit mode this required delay is 28 OCS
138 * clock cycles. For 256-bit mode it is 36 OCS clock cycles.
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/openbmc/linux/arch/powerpc/platforms/pasemi/
H A Ddma_lib.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2006-2007 PA Semi, Inc
5 * Common functions for DMA access on PA Semi PWRficient
43 /* pasemi_read_iob_reg - read IOB register
52 /* pasemi_write_iob_reg - write IOB register
53 * @reg: Register to write to (offset into PCI CFG space)
54 * @val: Value to write
62 /* pasemi_read_mac_reg - read MAC register
72 /* pasemi_write_mac_reg - write MAC register
74 * @reg: Register to write to (offset into PCI CFG space)
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/openbmc/qemu/tests/qemu-iotests/
H A D172.out11 dev: isa-fdc, id ""
14 dma = 2 (0x2)
18 bus: floppy-bus.0
19 type floppy-bus
29 write-cache = "auto"
30 share-rw = false
31 account-invalid = "auto"
32 account-failed = "auto"
33 drive-type = "288"
36 === Using -fda/-fdb options ===
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