| /openbmc/linux/include/dt-bindings/dma/ |
| H A D | dw-dmac.h | 1 /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
7 * Protection Control bits provide protection against illegal transactions.
8 * The protection bits[0:2] are one-to-one mapped to AHB HPROT[3:1] signals.
11 #define DW_DMAC_HPROT2_BUFFERABLE (1 << 1) /* DMA is bufferable */
12 #define DW_DMAC_HPROT3_CACHEABLE (1 << 2) /* DMA is cacheable */
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| /openbmc/linux/Documentation/arch/x86/ |
| H A D | intel_txt.rst | 6 Technology (Intel(R) TXT), defines platform-level enhancements that
13 - Provides dynamic root of trust for measurement (DRTM)
14 - Data protection in case of improper shutdown
15 - Measurement and verification of launched environment
18 non-vPro systems. It is currently available on desktop systems
30 - LinuxTAG 2008:
31 http://www.linuxtag.org/2008/en/conf/events/vp-donnerstag.html
33 - TRUST2008:
34 http://www.trust-conference.eu/downloads/Keynote-Speakers/
35 3_David-Grawrock_The-Front-Door-of-Trusted-Computing.pdf
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| /openbmc/linux/include/media/drv-intf/ |
| H A D | saa7146.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <linux/delay.h> /* for delay-stuff */
7 #include <linux/pci.h> /* for pci-config-stuff, vendor ids etc. */
16 #include <media/v4l2-device.h>
17 #include <media/v4l2-ctrls.h>
22 #define saa7146_write(sxy,adr,dat) writel((dat),(sxy->mem+(adr)))
23 #define saa7146_read(sxy,adr) readl(sxy->mem+(adr))
67 dma_addr_t dma; member
107 u32 irq_mask; /* mask to indicate, which irq-events are handled by the extension */
129 u32 revision; /* chip revision; needed for bug-workarounds*/
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| /openbmc/linux/Documentation/ABI/testing/ |
| H A D | sysfs-kernel-iommu_groups | 5 Description: /sys/kernel/iommu_groups/ contains a number of sub-
7 name of the sub-directory matches the iommu_group_id()
23 output direct-mapped, MSI, non mappable regions. Each
29 USB devices it is now exposed as "direct-relaxable" instead
43 DMA All the DMA transactions from the device in this group
45 DMA-FQ As above, but using batched invalidation to lazily
47 overhead at the cost of reduced memory protection.
48 identity All the DMA transactions from the device in this group
50 but zero protection.
56 - The device in the group is not bound to any device driver.
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| /openbmc/u-boot/drivers/dma/ |
| H A D | lpc32xx_dma.c | 1 // SPDX-License-Identifier: GPL-2.0+
5 * @Descr: LPC3250 DMA controller interface support functions
7 * Copyright (c) 2015 Tyco Fire Protection Products.
12 #include <asm/arch/dma.h>
18 /* DMA controller channel register structure */
23 u32 control; member
28 /* DMA controller register structures */
51 #define DMAC_CTRL_ENABLE (1 << 0) /* For enabling the DMA controller */
55 static struct dma_reg *dma = (struct dma_reg *)DMA_BASE; variable
63 * DMA clock are enable by "lpc32xx_dma_init()" and should in lpc32xx_dma_get_channel()
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| /openbmc/u-boot/doc/ |
| H A D | README.fsl-trustzone-components | 2 TZPC-BP147 (TrustZone Protection Controller) and TZASC-400 (TrustZone
6 is left to a root-of-trust security software layer (running in EL3
12 TZPC-BP147 (TrustZone Protection Controller)
14 - Depends on CONFIG_FSL_TZPC_BP147 configuration flag.
15 - Separates Secure World and Normal World on-chip RAM (OCRAM) spaces.
16 - Provides a programming model to set access control policy via the TZPC
19 TZASC-400 (TrustZone Address Space Controller)
21 - Depends on CONFIG_FSL_TZASC_400 configuration flag.
22 - Separates Secure World and Normal World external memory spaces for bus masters
23 such as processors and DMA-equipped peripherals.
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| /openbmc/linux/Documentation/devicetree/bindings/reserved-memory/ |
| H A D | shared-dma-pool.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/reserved-memory/shared-dma-pool.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: /reserved-memory DMA pool
10 - devicetree-spec@vger.kernel.org
13 - $ref: reserved-memory.yaml
18 - const: shared-dma-pool
21 pool of DMA buffers for a set of devices. It can be used by an
25 - const: restricted-dma-pool
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| /openbmc/u-boot/arch/powerpc/include/asm/ |
| H A D | processor.h | 19 #define MSR_UCLE (1<<26) /* User-mode cache lock enable (e500) */
43 #define MSR_PE (1<<3) /* Protection Enable */
44 #define MSR_PX (1<<2) /* Protection Exclusive Mode */
60 /* Floating Point Status and Control Register (FPSCR) Fields */
67 #define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */
70 #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
87 #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
88 #define FPSCR_RN 0x00000003 /* FPU rounding control */
96 #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
123 #define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
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| /openbmc/linux/arch/m68k/include/asm/ |
| H A D | m5407sim.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5407sim.h -- ColdFire 5407 System Integration Module support.
28 #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
60 #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
63 #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
66 #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
69 #define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
72 #define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
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| H A D | m5307sim.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5307sim.h -- ColdFire 5307 System Integration Module support.
28 #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
53 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
56 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
62 #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
64 #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
66 #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
68 #define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
70 #define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
[all …]
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| H A D | m5206sim.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m5206sim.h -- ColdFire 5206 System Integration Module support.
48 #define MCFSIM_SYPCR (MCF_MBAR + 0x41) /* System Protection */
57 #define MCFSIM_DCR0 (MCF_MBAR + 0x57) /* DRAM 0 Control reg (r/w) */
60 #define MCFSIM_DCR1 (MCF_MBAR + 0x63) /* DRAM 1 Control reg (r/w) */
64 #define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */
67 #define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */
70 #define MCFSIM_CSCR2 (MCF_MBAR + 0x86) /* CS 2 Control reg */
73 #define MCFSIM_CSCR3 (MCF_MBAR + 0x92) /* CS 3 Control reg */
76 #define MCFSIM_CSCR4 (MCF_MBAR + 0x9e) /* CS 4 Control reg */
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| H A D | m525xsim.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * m525xsim.h -- ColdFire 525x System Integration Module support.
36 #define MCFSIM_SYPCR (MCF_MBAR + 0x01) /* System Protection */
57 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
60 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
63 #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
66 #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
69 #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
71 #define MCFSIM_DCR (MCF_MBAR + 0x100) /* DRAM Control */
81 #define MCFINTC2_INTPRI1 (MCF_MBAR2 + 0x140) /* 0-7 priority */
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| /openbmc/linux/Documentation/admin-guide/sysctl/ |
| H A D | vm.rst | 13 ------------------------------------------------------------------------------
27 - admin_reserve_kbytes
28 - compact_memory
29 - compaction_proactiveness
30 - compact_unevictable_allowed
31 - dirty_background_bytes
32 - dirty_background_ratio
33 - dirty_bytes
34 - dirty_expire_centisecs
35 - dirty_ratio
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| /openbmc/openbmc/meta-phosphor/dynamic-layers/aspeed-layer/recipes-bsp/u-boot/files/ |
| H A D | 0001-aspeed-Disable-unnecessary-features.patch | 9 Upstream-Status: Pending
11 Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
12 ---
13 arch/arm/include/asm/arch-aspeed/regs-lpc.h | 29 +++++++++++
14 arch/arm/include/asm/arch-aspeed/regs-scu.h | 8 ++-
15 arch/arm/include/asm/arch-aspeed/regs-sdmc.h | 17 +++++++
16 board/aspeed/ast-g4/ast-g4.c | 46 ++++++++++++++++-
17 board/aspeed/ast-g5/ast-g5.c | 52 +++++++++++++++++++-
18 5 files changed, 149 insertions(+), 3 deletions(-)
19 create mode 100644 arch/arm/include/asm/arch-aspeed/regs-lpc.h
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| /openbmc/linux/drivers/dma/dw/ |
| H A D | of.c | 1 // SPDX-License-Identifier: GPL-2.0
3 * Platform driver for the Synopsys DesignWare DMA Controller
5 * Copyright (C) 2007-2008 Atmel Corporation
6 * Copyright (C) 2010-2011 ST Microelectronics
19 struct dw_dma *dw = ofdma->of_dma_data; in dw_dma_of_xlate()
21 .dma_dev = dw->dma.dev, in dw_dma_of_xlate()
25 if (dma_spec->args_count < 3 || dma_spec->args_count > 4) in dw_dma_of_xlate()
28 slave.src_id = dma_spec->args[0]; in dw_dma_of_xlate()
29 slave.dst_id = dma_spec->args[0]; in dw_dma_of_xlate()
30 slave.m_master = dma_spec->args[1]; in dw_dma_of_xlate()
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| /openbmc/linux/include/linux/platform_data/ |
| H A D | dma-dw.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Driver for the Synopsys DesignWare DMA Controller
6 * Copyright (C) 2010-2011 ST Microelectronics
22 * struct dw_dma_slave - Controller-specific information about a slave
24 * @dma_dev: required DMA master device
43 * struct dw_dma_platform_data - Controller configuration parameters
54 * @protctl: Protection control signals setting per channel.
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| /openbmc/linux/drivers/net/ethernet/altera/ |
| H A D | altera_tse.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /* Altera Triple-Speed Ethernet MAC driver
3 * Copyright (C) 2008-2014 Altera Corporation. All rights reserved
116 u32 control; /* PHY device operation control register */ member
120 u32 auto_negotiation_advertisement; /* Auto-negotiation
168 /* The host processor uses this register to control and configure the
172 /* 32-bit primary MAC address word 0 bits 0 to 31 of the primary
176 /* 32-bit primary MAC address word 1 bits 32 to 47 of the primary
180 /* 14-bit maximum frame length. The MAC receive logic */
186 /* 12-bit receive FIFO section-empty threshold */
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| /openbmc/linux/Documentation/devicetree/bindings/dma/ |
| H A D | snps,dma-spear1340.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
4 $id: http://devicetree.org/schemas/dma/snps,dma-spear1340.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys Designware DMA Controller
10 - Viresh Kumar <vireshk@kernel.org>
11 - Andy Shevchenko <andriy.shevchenko@linux.intel.com>
14 - $ref: dma-controller.yaml#
19 - const: snps,dma-spear1340
20 - items:
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| /openbmc/qemu/hw/audio/ |
| H A D | intel-hda-defs.h | 7 /* --------------------------------------------------------------------- */
25 #define ICH6_GCTL_FCNTRL (1 << 1) /* flush control */
41 #define ICH6_CORBCTL_RUN (1 << 1) /* enable DMA */
54 #define ICH6_RBCTL_DMA_EN (1 << 1) /* enable DMA */
113 /* max number of fragments - we may use more if allocating more pages for BDL */
117 /* max buffer size - no h/w limit, you can increase as you like */
128 #define STATESTS_INT_MASK ((1 << AZX_MAX_CODECS) - 1)
132 #define SD_CTL_DMA_START 0x02 /* stream DMA start bit */
133 #define SD_CTL_STRIPE (3 << 16) /* stripe control */
135 #define SD_CTL_DIR (1 << 19) /* bi-directional stream */
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| /openbmc/linux/Documentation/devicetree/bindings/pci/ |
| H A D | snps,dw-pcie.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/pci/snps,dw-pcie.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Jingoo Han <jingoohan1@gmail.com>
11 - Gustavo Pimentel <gustavo.pimentel@synopsys.com>
16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
17 # and make sure it's assigned with the vendor-specific compatible string.
21 const: snps,dw-pcie
23 - compatible
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| /openbmc/linux/drivers/net/ethernet/cortina/ |
| H A D | gemini.h | 1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt>
6 * Copyright (C) 2010 Michał Mirosław <mirq-linux@rere.qmqm.pl>
46 /* TOE DMA Queue Size should be 2^n, n = 6...12
47 * TOE DMA Queues are the following queue types:
49 * GMAC 0/1 SW TX Q0-5, and GMAC 0/1 HW TX Q0-5
51 * DMA Queues Descriptor Ring Base Address/Size Register (offset 0x0004)
58 #define __RWPTR_PREV(x, mask) (((unsigned int)(x) - 1) & (mask))
59 #define __RWPTR_DISTANCE(r, w, mask) (((unsigned int)(w) - (r)) & (mask))
60 #define __RWPTR_MASK(order) ((1 << (order)) - 1)
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| /openbmc/linux/Documentation/block/ |
| H A D | data-integrity.rst | 16 protocols (SBC Data Integrity Field, SCC protection proposal) as well
17 as SATA/T13 (External Path Protection) try to remedy this by adding
19 metadata (or protection information in SCSI terminology) includes a
22 for some protection schemes also that the I/O is written to the right
29 DIF and the other integrity extensions is that the protection format
42 the protection information to be transferred to and from their
45 The SCSI Data Integrity Field works by appending 8 bytes of protection
54 scatter-gather lists.
57 read. This means that Linux can DMA the data buffers to and from
60 Also, the 16-bit CRC checksum mandated by both the SCSI and SATA specs
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| /openbmc/linux/arch/arm/mm/ |
| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
17 A 32-bit RISC microprocessor based on the ARM7 processor core
18 which has no memory control unit and cache.
36 A 32-bit RISC processor with 8kByte Cache, Write Buffer and
53 A 32-bit RISC processor with 8KB cache or 4KB variants,
54 write buffer and MPU(Protection Unit) built around
69 A 32-bit RISC microprocessor based on the ARM9 processor core
70 which has no memory control unit and cache.
182 ARM940T is a member of the ARM9TDMI family of general-
184 instruction and 4KB data cases, each with a 4-word line
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| /openbmc/linux/Documentation/networking/device_drivers/ethernet/stmicro/ |
| H A D | stmmac.rst | 1 .. SPDX-License-Identifier: GPL-2.0+
13 - In This Release
14 - Feature List
15 - Kernel Configuration
16 - Command Line Parameters
17 - Driver Information and Notes
18 - Debug Information
19 - Support
33 (and older) and DesignWare(R) Cores Ethernet Quality-of-Service version 4.0
35 DesignWare(R) Cores XGMAC - 10G Ethernet MAC and DesignWare(R) Cores
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| /openbmc/linux/drivers/scsi/mvsas/ |
| H A D | mv_defs.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com>
28 /* driver compile-time configuration */
30 MVS_TX_RING_SZ = 1024, /* TX ring size (12-bit) */
31 MVS_RX_RING_SZ = 1024, /* RX ring size (12-bit) */
32 /* software requires power-of-2
44 MVS_SOC_CAN_QUEUE = MVS_SOC_SLOTS - 2,
58 SPI_CTL = 0x10, /* EEPROM control */
79 /* MVS_GBL_PORT_TYPE */ /* shl for ports 1-3 */
127 CINT_DMA_PCIE = (1U << 27), /* DMA to PCIE timeout */
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