| /openbmc/u-boot/tools/ |
| H A D | zynqmpimage.h | 46 uint32_t partition_header_offset; /* 0x08, divided by 4 */
47 uint32_t image_header_offset; /* 0x0c, divided by 4 */
99 uint32_t len_enc; /* 0x00, divided by 4 */
100 uint32_t len_unenc; /* 0x04, divided by 4 */
101 uint32_t len; /* 0x08, divided by 4 */
105 uint32_t offset; /* 0x20, divided by 4 */
108 uint32_t checksum_offset; /* 0x2c, divided by 4 */
|
| /openbmc/linux/Documentation/admin-guide/cgroup-v1/ |
| H A D | blkio-controller.rst | 152 are further divided by the type of operation - read or write, sync
159 are further divided by the type of operation - read or write, sync
172 io_service_time > actual time elapsed. This time is further divided by
188 devices too. This time is further divided by the type of operation -
195 cgroup. This is further divided by the type of operation - read or
200 cgroup. This is further divided by the type of operation - read or
285 are further divided by the type of operation - read or write, sync
292 are further divided by the type of operation - read or write, sync
|
| /openbmc/u-boot/include/cramfs/ |
| H A D | cramfs_fs.h | 33 /* NAMELEN is the length of the file name, divided by 4 and
36 contains the offset (divided by 4) of the file data in
39 (divided by 4) of the inode of the first file in that
|
| /openbmc/linux/include/uapi/linux/ |
| H A D | cramfs_fs.h | 34 /* NAMELEN is the length of the file name, divided by 4 and
37 contains the offset (divided by 4) of the file data in
40 (divided by 4) of the inode of the first file in that
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn10/ |
| H A D | rv1_clk_mgr.c | 51 /* already divided by 2, no need to reach target clk with 2 steps*/ in rv1_determine_dppclk_threshold()
61 /* target dpp clk not request divided by 2, still within threshold */ in rv1_determine_dppclk_threshold()
66 /* decrease clock, looking for current dppclk divided by 2, in rv1_determine_dppclk_threshold()
67 * request dppclk not divided by 2. in rv1_determine_dppclk_threshold()
70 /* current dpp clk not divided by 2, no need to ramp*/ in rv1_determine_dppclk_threshold()
80 /* request dpp clk need to be divided by 2 */ in rv1_determine_dppclk_threshold()
|
| /openbmc/qemu/include/hw/nvram/ |
| H A D | chrp_nvram.h | 27 uint16_t len; /* Big endian, length divided by 16 */
40 /* Length divided by 16 */ in chrp_nvram_finish_partition()
|
| /openbmc/linux/Documentation/userspace-api/media/drivers/ |
| H A D | cx2341x-uapi.rst | 18 The Y plane is divided into blocks of 16x16 pixels from left to right
26 The UV plane is divided into blocks of 16x8 UV values going from left
65 // The Y plane is divided into blocks of 16x16 pixels
84 // Again, the UV plane is divided into blocks of 16x16 UV values.
|
| /openbmc/linux/Documentation/userspace-api/media/v4l/ |
| H A D | ext-ctrls-detect.rst | 37 - The image is divided into a grid, each cell with its own motion
41 - The image is divided into a grid, each cell with its own region
|
| /openbmc/linux/arch/arm/boot/dts/arm/ |
| H A D | integratorcp.dts | 56 /* The chrystal is divided by 2 by the codec for the AACI bit clock */
72 /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */
124 /* The KMI clock is the 24 MHz oscillator divided to 8MHz */
133 /* The timer clock is the 24 MHz oscillator divided to 1MHz */
|
| /openbmc/linux/arch/powerpc/platforms/8xx/ |
| H A D | m8xx_setup.c | 61 /* The decrementer counts at the system (internal) clock frequency divided by
62 * sixteen, or external oscillator divided by four. We force the processor
63 * to use system clock divided by sixteen.
|
| /openbmc/linux/drivers/powercap/ |
| H A D | Kconfig | 33 In RAPL, the platform level settings are divided into domains for
48 In RAPL, the platform level settings are divided into domains for
|
| /openbmc/linux/drivers/clk/ingenic/ |
| H A D | jz4760-cgu.c | 201 /* Divided clocks */
212 /* Those divided clocks can connect to PLL0 or PLL1 */
254 /* Those divided clocks can connect to EXT, PLL0 or PLL1 */
280 /* Those divided clocks can connect to EXT or PLL0 */
294 /* These divided clock can connect to PLL0 only */
|
| /openbmc/linux/tools/perf/pmu-events/arch/x86/silvermont/ |
| H A D | virtual-memory.json | 23 …-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page…
40 …ue to an instruction fetch) page walk is in progress. Page walk duration divided by number of page…
|
| /openbmc/linux/drivers/clk/mvebu/ |
| H A D | ap806-system-controller.c | 200 /* MSS Clock is fixed clock divided by 6 */ in ap806_syscon_common_probe()
209 /* SDIO(/eMMC) Clock is fixed clock divided by 3 */ in ap806_syscon_common_probe()
219 /* AP-DCLK(HCLK) Clock is DDR clock divided by 2 */ in ap806_syscon_common_probe()
|
| /openbmc/linux/Documentation/w1/slaves/ |
| H A D | w1_ds2438.rst | 70 Important: The returned value has to be divided by 256 to get a real
86 Note: To get a volts the value has to be divided by 100.
|
| /openbmc/linux/Documentation/devicetree/bindings/sound/ |
| H A D | nvidia,tegra210-admaif.yaml | 66 DMA channel specifiers, equally divided for Tx and Rx.
82 DMA channel specifiers, equally divided for Tx and Rx.
|
| /openbmc/linux/drivers/gpu/drm/amd/display/dc/dcn21/ |
| H A D | dcn21_dccg.c | 64 * ceiling phase and truncate modulo guarentees the divided in dccg21_update_dpp_dto()
72 * in these case we don't want pipe clock to be divided in dccg21_update_dpp_dto()
|
| /openbmc/qemu/hw/ipack/ |
| H A D | tpci200.c | 318 * The address is divided into the IP module number (0-4), the IP in tpci200_read_las1()
380 * The address is divided into the IP module number, the IP in tpci200_write_las1()
428 * The address is divided into the IP module number and the offset in tpci200_read_las2()
459 * The address is divided into the IP module number and the offset in tpci200_write_las2()
482 * The address is divided into the IP module number and the offset in tpci200_read_las3()
508 * The address is divided into the IP module number and the offset in tpci200_write_las3()
|
| /openbmc/linux/drivers/comedi/drivers/ |
| H A D | plx9080.h | 553 /* DMA Channel 0 PCI-to-Local Almost Full (divided by 2, minus 1) */
557 /* DMA Channel 0 Local-to-PCI Almost Empty (divided by 2, minus 1) */
561 /* DMA Channel 0 Local-to-PCI Almost Full (divided by 2, minus 1) */
565 /* DMA Channel 0 PCI-to-Local Almost Empty (divided by 2, minus 1) */
569 /* DMA Channel 1 PCI-to-Local Almost Full (divided by 2, minus 1) */
573 /* DMA Channel 1 Local-to-PCI Almost Empty (divided by 2, minus 1) */
577 /* DMA Channel 1 Local-to-PCI Almost Full (divided by 2, minus 1) */
581 /* DMA Channel 1 PCI-to-Local Almost Empty (divided by 2, minus 1) */
|
| /openbmc/linux/drivers/staging/media/atomisp/pci/ |
| H A D | css_trace.h | 101 /* currently divided as follows:*/
103 /* can be divided as needed */
151 #error trace sizes are not divided correctly and are above limit
|
| /openbmc/linux/Documentation/networking/ |
| H A D | nfc.rst | 19 The subsystem is divided in some parts. The 'core' is responsible for
71 The userspace interface is divided in control operations and low-level data
|
| /openbmc/qemu/hw/ppc/ |
| H A D | pnv_nest_pervasive.c | 22 * A POWER10 chip is divided into logical units called chiplets. Chiplets
23 * are broadly divided into "core chiplets" (with the processor cores) and
|
| /openbmc/linux/Documentation/dev-tools/kunit/api/ |
| H A D | index.rst | 14 This page documents the KUnit kernel testing API. It is divided into the
|
| /openbmc/linux/arch/arm/mach-ep93xx/ |
| H A D | hardware.h | 15 * higher frequencies that are then divided down by programmable dividers
|
| /openbmc/openbmc/poky/documentation/test-manual/ |
| H A D | yocto-project-compatible.rst | 87 Layers are divided into three types:
110 be internally divided into sublayers to separate these components.
|