11b097845SAndi Kleen[ 21b097845SAndi Kleen { 3*a2f6001bSIan Rogers "BriefDescription": "Loads missed DTLB", 4*a2f6001bSIan Rogers "EventCode": "0x04", 5*a2f6001bSIan Rogers "EventName": "MEM_UOPS_RETIRED.DTLB_MISS_LOADS", 61b097845SAndi Kleen "PEBS": "1", 71b097845SAndi Kleen "PublicDescription": "This event counts the number of load ops retired that had DTLB miss.", 81b097845SAndi Kleen "SampleAfterValue": "200003", 9*a2f6001bSIan Rogers "UMask": "0x8" 101b097845SAndi Kleen }, 111b097845SAndi Kleen { 12*a2f6001bSIan Rogers "BriefDescription": "Total cycles for all the page walks. (I-side and D-side)", 131b097845SAndi Kleen "EventCode": "0x05", 141b097845SAndi Kleen "EventName": "PAGE_WALKS.CYCLES", 15*a2f6001bSIan Rogers "PublicDescription": "This event counts every cycle when a data (D) page walk or instruction (I) page walk is in progress. Since a pagewalk implies a TLB miss, the approximate cost of a TLB miss can be determined from this event.", 161b097845SAndi Kleen "SampleAfterValue": "200003", 17*a2f6001bSIan Rogers "UMask": "0x3" 18*a2f6001bSIan Rogers }, 19*a2f6001bSIan Rogers { 20*a2f6001bSIan Rogers "BriefDescription": "Duration of D-side page-walks in core cycles", 21*a2f6001bSIan Rogers "EventCode": "0x05", 22*a2f6001bSIan Rogers "EventName": "PAGE_WALKS.D_SIDE_CYCLES", 23*a2f6001bSIan Rogers "PublicDescription": "This event counts every cycle when a D-side (walks due to a load) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.", 24*a2f6001bSIan Rogers "SampleAfterValue": "200003", 25*a2f6001bSIan Rogers "UMask": "0x1" 26*a2f6001bSIan Rogers }, 27*a2f6001bSIan Rogers { 28*a2f6001bSIan Rogers "BriefDescription": "D-side page-walks", 29*a2f6001bSIan Rogers "EdgeDetect": "1", 30*a2f6001bSIan Rogers "EventCode": "0x05", 31*a2f6001bSIan Rogers "EventName": "PAGE_WALKS.D_SIDE_WALKS", 32*a2f6001bSIan Rogers "PublicDescription": "This event counts when a data (D) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.", 33*a2f6001bSIan Rogers "SampleAfterValue": "100003", 34*a2f6001bSIan Rogers "UMask": "0x1" 35*a2f6001bSIan Rogers }, 36*a2f6001bSIan Rogers { 37*a2f6001bSIan Rogers "BriefDescription": "Duration of I-side page-walks in core cycles", 38*a2f6001bSIan Rogers "EventCode": "0x05", 39*a2f6001bSIan Rogers "EventName": "PAGE_WALKS.I_SIDE_CYCLES", 40*a2f6001bSIan Rogers "PublicDescription": "This event counts every cycle when a I-side (walks due to an instruction fetch) page walk is in progress. Page walk duration divided by number of page walks is the average duration of page-walks.", 41*a2f6001bSIan Rogers "SampleAfterValue": "200003", 42*a2f6001bSIan Rogers "UMask": "0x2" 43*a2f6001bSIan Rogers }, 44*a2f6001bSIan Rogers { 45*a2f6001bSIan Rogers "BriefDescription": "I-side page-walks", 46*a2f6001bSIan Rogers "EdgeDetect": "1", 47*a2f6001bSIan Rogers "EventCode": "0x05", 48*a2f6001bSIan Rogers "EventName": "PAGE_WALKS.I_SIDE_WALKS", 49*a2f6001bSIan Rogers "PublicDescription": "This event counts when an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.", 50*a2f6001bSIan Rogers "SampleAfterValue": "100003", 51*a2f6001bSIan Rogers "UMask": "0x2" 52*a2f6001bSIan Rogers }, 53*a2f6001bSIan Rogers { 54*a2f6001bSIan Rogers "BriefDescription": "Total page walks that are completed (I-side and D-side)", 55*a2f6001bSIan Rogers "EdgeDetect": "1", 56*a2f6001bSIan Rogers "EventCode": "0x05", 57*a2f6001bSIan Rogers "EventName": "PAGE_WALKS.WALKS", 58*a2f6001bSIan Rogers "PublicDescription": "This event counts when a data (D) page walk or an instruction (I) page walk is completed or started. Since a page walk implies a TLB miss, the number of TLB misses can be counted by counting the number of pagewalks.", 59*a2f6001bSIan Rogers "SampleAfterValue": "100003", 60*a2f6001bSIan Rogers "UMask": "0x3" 611b097845SAndi Kleen } 621b097845SAndi Kleen] 63