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/openbmc/u-boot/arch/mips/mach-mt7620/
H A DKconfig4 config SYS_MALLOC_F_LEN
7 config SYS_SOC
13 config SOC_MT7620
24 config BOARD_GARDENA_SMART_GATEWAY_MT7688
33 config BOARD_LINKIT_SMART_7688
49 config BOOT_RAM
57 config BOOT_ROM
70 config ONBOARD_DDR2_SIZE_256MBIT
74 Use 256MBit (32MByte) of DDR total size
76 config ONBOARD_DDR2_SIZE_512MBIT
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/openbmc/u-boot/board/freescale/ls1012ardb/
H A DKconfig3 config SYS_BOARD
6 config SYS_VENDOR
9 config SYS_SOC
10 default "fsl-layerscape"
12 config SYS_CONFIG_NAME
15 config SYS_LS_PPA_FW_ADDR
20 config SYS_LS_PPA_ESBC_ADDR
27 config BOARD_SPECIFIC_OPTIONS # dummy
32 config SYS_LS_PFE_FW_ADDR
36 config SYS_LS_PFE_ESBC_ADDR
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/openbmc/u-boot/drivers/ddr/fsl/
H A DKconfig1 config SYS_FSL_DDR
4 Select Freescale General DDR driver, shared between most Freescale
5 PowerPC- based SoCs (such as mpc83xx, mpc85xx, mpc86xx) and ARM-
8 config SYS_FSL_MMDC
11 Select Freescale Multi Mode DDR controller (MMDC).
13 config SYS_FSL_DDR_BE
16 Access DDR registers in big-endian
18 config SYS_FSL_DDR_LE
21 Access DDR registers in little-endian
23 config FSL_DDR_BIST
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H A Darm_ddr_gen3.c1 // SPDX-License-Identifier: GPL-2.0+
22 * regs has the to-be-set values for DDR controller registers
23 * ctrl_num is the DDR controller number
27 * Dividing the initialization to two steps to deassert DDR reset signal
34 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
41 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_set_memctl_regs()
45 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_set_memctl_regs()
50 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in fsl_ddr_set_memctl_regs()
55 ddr = (void *)CONFIG_SYS_FSL_DDR4_ADDR; in fsl_ddr_set_memctl_regs()
66 if (regs->ddr_eor) in fsl_ddr_set_memctl_regs()
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H A Dfsl_ddr_gen4.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2014-2015 Freescale Semiconductor, Inc.
30 timeout--; in set_wait_for_bits_clear()
42 * regs has the to-be-set values for DDR controller registers
43 * ctrl_num is the DDR controller number
47 * Dividing the initialization to two steps to deassert DDR reset signal
54 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
75 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_set_memctl_regs()
79 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_set_memctl_regs()
84 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in fsl_ddr_set_memctl_regs()
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H A Dmpc85xx_ddr_gen3.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2008-2012 Freescale Semiconductor, Inc.
16 * regs has the to-be-set values for DDR controller registers
17 * ctrl_num is the DDR controller number
21 * Dividing the initialization to two steps to deassert DDR reset signal
28 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
36 int csn = -1; in fsl_ddr_set_memctl_regs()
44 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_set_memctl_regs()
48 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_set_memctl_regs()
53 ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; in fsl_ddr_set_memctl_regs()
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H A Dmpc86xx_ddr.c1 // SPDX-License-Identifier: GPL-2.0
18 struct ccsr_ddr __iomem *ddr; in fsl_ddr_set_memctl_regs() local
22 ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; in fsl_ddr_set_memctl_regs()
25 ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; in fsl_ddr_set_memctl_regs()
34 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
35 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
38 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
39 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
42 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
43 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
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H A Dmpc85xx_ddr_gen1.c1 // SPDX-License-Identifier: GPL-2.0
18 struct ccsr_ddr __iomem *ddr = in fsl_ddr_set_memctl_regs() local
28 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
29 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
32 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
33 out_be32(&ddr->cs1_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
36 out_be32(&ddr->cs2_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
37 out_be32(&ddr->cs2_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
40 out_be32(&ddr->cs3_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
41 out_be32(&ddr->cs3_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
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H A Dmpc85xx_ddr_gen2.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2008-2011 Freescale Semiconductor, Inc.
19 struct ccsr_ddr __iomem *ddr = in fsl_ddr_set_memctl_regs() local
34 * Set the DDR IO receiver to an acceptable bias point. in fsl_ddr_set_memctl_regs()
39 if ((regs->ddr_sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) == in fsl_ddr_set_memctl_regs()
41 out_be32(&gur->ddrioovcr, 0x90000000); in fsl_ddr_set_memctl_regs()
43 out_be32(&gur->ddrioovcr, 0xA8000000); in fsl_ddr_set_memctl_regs()
49 out_be32(&ddr->cs0_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
50 out_be32(&ddr->cs0_config, regs->cs[i].config); in fsl_ddr_set_memctl_regs()
53 out_be32(&ddr->cs1_bnds, regs->cs[i].bnds); in fsl_ddr_set_memctl_regs()
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/openbmc/u-boot/board/freescale/ls1012aqds/
H A DKconfig3 config SYS_BOARD
6 config SYS_VENDOR
9 config SYS_SOC
10 default "fsl-layerscape"
12 config SYS_CONFIG_NAME
15 config SYS_LS_PPA_FW_ADDR
20 config SYS_LS_PPA_ESBC_ADDR
27 config BOARD_SPECIFIC_OPTIONS # dummy
35 config PFE_RGMII_RESET_WA
38 config SYS_LS_PFE_FW_ADDR
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/openbmc/u-boot/arch/arm/mach-uniphier/
H A DKconfig3 config SYS_CONFIG_NAME
6 config ARCH_UNIPHIER_32BIT
17 config ARCH_UNIPHIER_LD4_SLD8
21 config ARCH_UNIPHIER_V7_MULTI
25 config ARCH_UNIPHIER_V8_MULTI
33 config ARCH_UNIPHIER_LD4
38 config ARCH_UNIPHIER_SLD8
43 config ARCH_UNIPHIER_PRO4
48 config ARCH_UNIPHIER_PRO5
53 config ARCH_UNIPHIER_PXS2
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/openbmc/u-boot/board/freescale/ls1012afrdm/
H A DKconfig3 config SYS_BOARD
6 config SYS_VENDOR
9 config SYS_SOC
10 default "fsl-layerscape"
12 config SYS_CONFIG_NAME
15 config SYS_LS_PFE_FW_ADDR
19 config SYS_LS_PPA_FW_ADDR
26 config BOARD_SPECIFIC_OPTIONS # dummy
32 config DDR_PFE_PHYS_BASEADDR
33 hex "PFE DDR physical base address"
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/openbmc/u-boot/board/freescale/mx6memcal/
H A DKconfig3 config SYS_BOARD
6 config SYS_VENDOR
9 config SYS_CONFIG_NAME
19 config SERIAL_CONSOLE_UART1
24 config SERIAL_CONSOLE_UART2
38 config UART2_EIM_D26_27
47 config UART1_CSI0_DAT10_11
55 config UART1_UART1
65 config IMXIMAGE_OUTPUT
69 Say "Y" if you want output formatted for use in non-SPL
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/openbmc/linux/drivers/perf/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
9 config ARM_CCI_PMU
17 If compiled as a module, it will be called arm-cci.
19 config ARM_CCI400_PMU
20 bool "support CCI-400"
25 CCI-400 provides 4 independent event counters counting events related
28 config ARM_CCI5xx_PMU
29 bool "support CCI-500/CCI-550"
33 CCI-500/CCI-550 both provide 8 independent event counters, which can
37 config ARM_CCN
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/openbmc/u-boot/arch/arm/mach-zynqmp/
H A DKconfig3 config SPL_FS_FAT
6 config SPL_LIBCOMMON_SUPPORT
9 config SPL_LIBDISK_SUPPORT
12 config SPL_LIBGENERIC_SUPPORT
15 config SPL_MMC_SUPPORT
18 config SPL_SERIAL_SUPPORT
21 config SPL_SPI_FLASH_SUPPORT
24 config SPL_SPI_SUPPORT
27 config SYS_BOARD
30 config SYS_VENDOR
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/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A DKconfig3 config TARGET_TI816X_EVM
13 config TARGET_TI814X_EVM
23 config AM33XX_CHILISOM
30 config TARGET_AM335X_EVM
65 config TARGET_AM335X_BALTOS
73 config TARGET_AM335X_IGEP003X
81 config TARGET_AM335X_SHC
90 config TARGET_AM335X_SL50
98 config TARGET_BAV335X
107 incorporates the popular Texas Instruments Sitara 32bit ARM Coretex-A8
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/openbmc/u-boot/arch/arm/mach-zynq/
H A DKconfig3 config SPL_LDSCRIPT
4 default "arch/arm/mach-zynq/u-boot-spl.lds"
6 config SPL_FS_FAT
9 config SPL_LIBCOMMON_SUPPORT
12 config SPL_LIBDISK_SUPPORT
15 config SPL_LIBGENERIC_SUPPORT
18 config SPL_MMC_SUPPORT
21 config SPL_SERIAL_SUPPORT
24 config SPL_SPI_FLASH_SUPPORT
27 config SPL_SPI_SUPPORT
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/openbmc/linux/drivers/memory/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
11 for DRAM (SDR, DDR), ROM, SRAM and others. The drivers features
17 config DDR config
20 Data from JEDEC specs for DDR SDRAM memories,
23 DDR SDRAM controllers.
25 config ARM_PL172_MPMC
33 config ATMEL_EBI
42 Used to configure the EBI (external bus interface) when the device-
46 config BRCMSTB_DPFE
52 STB SoCs. The firmware running on the DCPU inside the DDR PHY can
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/openbmc/u-boot/drivers/ram/stm32mp1/
H A Dstm32mp1_ddr.h1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
17 /* DDR CTL and DDR PHY REGISTERS */
26 * @ctl: DDR controleur base address
27 * @clk: DDR clock
28 * @phy: DDR PHY base address
184 const struct stm32mp1_ddr_config *config);
193 int stm32mp1_dump_param(const struct stm32mp1_ddr_config *config,
196 void stm32mp1_edit_param(const struct stm32mp1_ddr_config *config,
202 const struct stm32mp1_ddr_config *config);
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H A Dstm32mp1_ram.c1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
32 ret = clk_get_by_name(priv->dev, clkname[idx], &clk); in stm32mp1_ddr_clk_enable()
43 priv->clk = clk; in stm32mp1_ddr_clk_enable()
44 ddrphy_clk = clk_get_rate(&priv->clk); in stm32mp1_ddr_clk_enable()
46 debug("DDR: mem_speed (%d MHz), RCC %d MHz\n", in stm32mp1_ddr_clk_enable()
49 ddr_clk = abs(ddrphy_clk - mem_speed * 1000 * 1000); in stm32mp1_ddr_clk_enable()
51 pr_err("DDR expected freq %d MHz, current is %d MHz\n", in stm32mp1_ddr_clk_enable()
53 return -EINVAL; in stm32mp1_ddr_clk_enable()
64 struct stm32mp1_ddr_config config; in stm32mp1_ddr_setup() local
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/openbmc/u-boot/board/tqc/tqm834x/
H A Dtqm834x.c1 // SPDX-License-Identifier: GPL-2.0+
46 static void set_cs_config(short cs, long config);
58 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im) in board_early_init_r()
75 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE; in dram_init()
76 im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G); in dram_init()
87 /* configure ddr controller */ in dram_init()
92 /* enable DDR controller */ in dram_init()
93 im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN | in dram_init()
108 debug("DDR Bank%d size: %ld MiB\n\n", cs, bank_size >> 20); in dram_init()
114 gd->ram_size = size; in dram_init()
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/openbmc/u-boot/board/ti/common/
H A Dboard_detect.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com
23 * struct ti_am_eeprom - This structure holds data read in from the
29 * @config: Reserved
35 * TI boards with a single MLO and u-boot.
42 char config[TI_EEPROM_HDR_CONFIG_LEN]; member
52 * struct dra7_eeprom - This structure holds data read in from the DRA7 EVM
58 * @config: Board specific config options
59 * @emif1_size: Size of DDR attached to EMIF1
60 * @emif2_size: Size of DDR attached to EMIF2
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/openbmc/linux/drivers/regulator/
H A Dbd9571mwv-regulator.c1 // SPDX-License-Identifier: GPL-2.0
3 * ROHM BD9571MWV-M and BD9574MWF-M regulator driver
12 #include <linux/mfd/rohm-generic.h>
23 /* DDR Backup Power */
24 u8 bkup_mode_cnt_keepon; /* from "rohm,ddr-backup-power" */
57 ret = regmap_read(rdev->regmap, BD9571MWV_AVS_SET_MONI, &val); in bd9571mwv_avs_get_moni_state()
73 return regmap_write_bits(rdev->regmap, BD9571MWV_AVS_VD09_VID(ret), in bd9571mwv_avs_set_voltage_sel_regmap()
74 rdev->desc->vsel_mask, sel); in bd9571mwv_avs_set_voltage_sel_regmap()
86 ret = regmap_read(rdev->regmap, BD9571MWV_AVS_VD09_VID(ret), &val); in bd9571mwv_avs_get_voltage_sel_regmap()
90 val &= rdev->desc->vsel_mask; in bd9571mwv_avs_get_voltage_sel_regmap()
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/openbmc/linux/drivers/edac/
H A DKconfig6 config EDAC_ATOMIC_SCRUB
9 config EDAC_SUPPORT
16 EDAC is a subsystem along with hardware-specific drivers designed to
17 report hardware errors. These are low-level errors that are reported
22 The mailing list for the EDAC project is linux-edac@vger.kernel.org.
26 config EDAC_LEGACY_SYSFS
34 config EDAC_DEBUG
40 levels are 0-4 (from low to high) and by default it is set to 2.
43 config EDAC_DECODE_MCE
44 tristate "Decode MCEs in human-readable form (only on AMD for now)"
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/openbmc/u-boot/include/configs/
H A Dx600.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2009, STMicroelectronics - All Rights Reserved
44 /* NOR FLASH config options */
54 /* NAND FLASH config options */
64 /* UBI/UBI config options */
66 /* Ethernet config options */
71 /* I2C config options */
80 /* FPGA config options */
88 * U-Boot Environment placing definitions.
115 "u-boot_addr=1000000\0" \
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