| /openbmc/linux/Documentation/arch/loongarch/ |
| H A D | irq-chip-model.rst | 8 with LS7A chipsets. The irq chips in LoongArch computers include CPUINTC (CPU Core
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
23 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
25 to LIOINTC, and then CPUINTC::
28 | IPI | --> | CPUINTC | <-- | Timer |
60 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
62 to CPUINTC directly::
65 | IPI | --> | CPUINTC | <-- | Timer |
91 CPUINTC::
149 - CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described
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| /openbmc/linux/arch/mips/boot/dts/realtek/ |
| H A D | rtl83xx.dtsi | 12 cpuintc: cpuintc { label
31 interrupt-parent = <&cpuintc>;
48 interrupt-parent = <&cpuintc>;
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| /openbmc/linux/arch/mips/boot/dts/ralink/ |
| H A D | mt7620a.dtsi | 13 cpuintc: cpuintc { label
40 interrupt-parent = <&cpuintc>;
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| H A D | rt2880.dtsi | 13 cpuintc: cpuintc { label
40 interrupt-parent = <&cpuintc>;
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| H A D | rt3883.dtsi | 13 cpuintc: cpuintc { label
40 interrupt-parent = <&cpuintc>;
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| H A D | rt3050.dtsi | 13 cpuintc: cpuintc { label
40 interrupt-parent = <&cpuintc>;
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| H A D | mt7628a.dtsi | 24 cpuintc: interrupt-controller { label
160 interrupt-parent = <&cpuintc>;
293 interrupt-parent = <&cpuintc>;
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| /openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/ |
| H A D | google,goldfish-pic.txt | 14 cpuintc {
28 interrupt-parent = <&cpuintc>;
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| H A D | qca,ath79-misc-intc.txt | 27 interrupt-parent = <&cpuintc>;
40 interrupt-parent = <&cpuintc>;
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| /openbmc/linux/Documentation/translations/zh_CN/arch/loongarch/ |
| H A D | irq-chip-model.rst | 31 | IPI | --> | CPUINTC | <-- | Timer |
67 | IPI | --> | CPUINTC | <-- | Timer |
93 CPUINTC::
151 - CPUINTC：即《龙芯架构参考手册卷一》第7.4节所描述的CSR.ECFG/CSR.ESTAT寄存器及其
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| /openbmc/linux/arch/mips/boot/dts/qca/ |
| H A D | ar9132.dtsi | 22 cpuintc: interrupt-controller { label
40 interrupt-parent = <&cpuintc>;
116 interrupt-parent = <&cpuintc>;
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| H A D | ar9331.dtsi | 22 cpuintc: interrupt-controller { label
44 interrupt-parent = <&cpuintc>;
104 interrupt-parent = <&cpuintc>;
|
| /openbmc/linux/arch/mips/boot/dts/loongson/ |
| H A D | loongson64g-package.dtsi | 9 cpuintc: interrupt-controller { label
31 interrupt-parent = <&cpuintc>;
|
| H A D | loongson64c-package.dtsi | 9 cpuintc: interrupt-controller { label
34 interrupt-parent = <&cpuintc>;
|
| H A D | loongson64v_4core_virtio.dts | 11 cpuintc: interrupt-controller { label
33 interrupt-parent = <&cpuintc>;
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| /openbmc/linux/arch/mips/boot/dts/mscc/ |
| H A D | luton.dtsi | 25 cpuintc: interrupt-controller { label
64 interrupt-parent = <&cpuintc>;
|
| H A D | serval.dtsi | 28 cpuintc: interrupt-controller { label
67 interrupt-parent = <&cpuintc>;
|
| H A D | jaguar2.dtsi | 29 cpuintc: interrupt-controller { label
68 interrupt-parent = <&cpuintc>;
|
| /openbmc/linux/drivers/irqchip/ |
| H A D | irq-loongarch-cpu.c | 67 .name = "CPUINTC",
158 cpuintc_handle = irq_domain_alloc_named_fwnode("CPUINTC"); in cpuintc_acpi_init()
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| /openbmc/linux/arch/mips/boot/dts/xilfpga/ |
| H A D | nexys4ddr.dts | 22 cpuintc: interrupt-controller { label
37 interrupt-parent = <&cpuintc>;
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| /openbmc/u-boot/arch/mips/dts/ |
| H A D | mscc,serval.dtsi | 27 cpuintc: interrupt-controller@0 { label
70 interrupt-parent = <&cpuintc>;
|
| H A D | jz4780.dtsi | 10 cpuintc: interrupt-controller { label
24 interrupt-parent = <&cpuintc>;
|
| H A D | mscc,servalt.dtsi | 27 cpuintc: interrupt-controller@0 { label
70 interrupt-parent = <&cpuintc>;
|
| H A D | mt7628a.dtsi | 24 cpuintc: interrupt-controller { label
72 interrupt-parent = <&cpuintc>;
|
| H A D | mscc,jr2.dtsi | 27 cpuintc: interrupt-controller@0 { label
64 interrupt-parent = <&cpuintc>;
|