Home
last modified time | relevance | path

Searched full:cpuintc (Results 1 – 25 of 49) sorted by relevance

12

/openbmc/linux/Documentation/arch/loongarch/
H A Dirq-chip-model.rst8 with LS7A chipsets. The irq chips in LoongArch computers include CPUINTC (CPU Core
14 CPUINTC is a per-core controller (in CPU), LIOINTC/EIOINTC/HTVECINTC are per-package
23 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
25 to LIOINTC, and then CPUINTC::
28 | IPI | --> | CPUINTC | <-- | Timer |
60 to CPUINTC directly, CPU UARTS interrupts go to LIOINTC, while all other devices
62 to CPUINTC directly::
65 | IPI | --> | CPUINTC | <-- | Timer |
91 CPUINTC::
149 - CPUINTC is CSR.ECFG/CSR.ESTAT and its interrupt controller described
/openbmc/linux/arch/mips/boot/dts/realtek/
H A Drtl83xx.dtsi12 cpuintc: cpuintc { label
31 interrupt-parent = <&cpuintc>;
48 interrupt-parent = <&cpuintc>;
/openbmc/linux/arch/mips/boot/dts/ralink/
H A Dmt7620a.dtsi13 cpuintc: cpuintc { label
40 interrupt-parent = <&cpuintc>;
H A Drt2880.dtsi13 cpuintc: cpuintc { label
40 interrupt-parent = <&cpuintc>;
H A Drt3883.dtsi13 cpuintc: cpuintc { label
40 interrupt-parent = <&cpuintc>;
H A Drt3050.dtsi13 cpuintc: cpuintc { label
40 interrupt-parent = <&cpuintc>;
H A Dmt7628a.dtsi24 cpuintc: interrupt-controller { label
160 interrupt-parent = <&cpuintc>;
293 interrupt-parent = <&cpuintc>;
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dgoogle,goldfish-pic.txt14 cpuintc {
28 interrupt-parent = <&cpuintc>;
H A Dqca,ath79-misc-intc.txt27 interrupt-parent = <&cpuintc>;
40 interrupt-parent = <&cpuintc>;
/openbmc/linux/Documentation/translations/zh_CN/arch/loongarch/
H A Dirq-chip-model.rst31 | IPI | --> | CPUINTC | <-- | Timer |
67 | IPI | --> | CPUINTC | <-- | Timer |
93 CPUINTC::
151 - CPUINTC:即《龙芯架构参考手册卷一》第7.4节所描述的CSR.ECFG/CSR.ESTAT寄存器及其
/openbmc/linux/arch/mips/boot/dts/qca/
H A Dar9132.dtsi22 cpuintc: interrupt-controller { label
40 interrupt-parent = <&cpuintc>;
116 interrupt-parent = <&cpuintc>;
H A Dar9331.dtsi22 cpuintc: interrupt-controller { label
44 interrupt-parent = <&cpuintc>;
104 interrupt-parent = <&cpuintc>;
/openbmc/linux/arch/mips/boot/dts/loongson/
H A Dloongson64g-package.dtsi9 cpuintc: interrupt-controller { label
31 interrupt-parent = <&cpuintc>;
H A Dloongson64c-package.dtsi9 cpuintc: interrupt-controller { label
34 interrupt-parent = <&cpuintc>;
H A Dloongson64v_4core_virtio.dts11 cpuintc: interrupt-controller { label
33 interrupt-parent = <&cpuintc>;
/openbmc/linux/arch/mips/boot/dts/mscc/
H A Dluton.dtsi25 cpuintc: interrupt-controller { label
64 interrupt-parent = <&cpuintc>;
H A Dserval.dtsi28 cpuintc: interrupt-controller { label
67 interrupt-parent = <&cpuintc>;
H A Djaguar2.dtsi29 cpuintc: interrupt-controller { label
68 interrupt-parent = <&cpuintc>;
/openbmc/linux/drivers/irqchip/
H A Dirq-loongarch-cpu.c67 .name = "CPUINTC",
158 cpuintc_handle = irq_domain_alloc_named_fwnode("CPUINTC"); in cpuintc_acpi_init()
/openbmc/linux/arch/mips/boot/dts/xilfpga/
H A Dnexys4ddr.dts22 cpuintc: interrupt-controller { label
37 interrupt-parent = <&cpuintc>;
/openbmc/u-boot/arch/mips/dts/
H A Dmscc,serval.dtsi27 cpuintc: interrupt-controller@0 { label
70 interrupt-parent = <&cpuintc>;
H A Djz4780.dtsi10 cpuintc: interrupt-controller { label
24 interrupt-parent = <&cpuintc>;
H A Dmscc,servalt.dtsi27 cpuintc: interrupt-controller@0 { label
70 interrupt-parent = <&cpuintc>;
H A Dmt7628a.dtsi24 cpuintc: interrupt-controller { label
72 interrupt-parent = <&cpuintc>;
H A Dmscc,jr2.dtsi27 cpuintc: interrupt-controller@0 { label
64 interrupt-parent = <&cpuintc>;

12