1bb35586fSAlban BedelBinding for Qualcomm Atheros AR7xxx/AR9XXX MISC interrupt controller 2bb35586fSAlban Bedel 3bb35586fSAlban BedelThe MISC interrupt controller is a secondary controller for lower priority 4bb35586fSAlban Bedelinterrupt. 5bb35586fSAlban Bedel 6bb35586fSAlban BedelRequired Properties: 719446da4SAlexander Couzens- compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or 819446da4SAlexander Couzens "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc" 9bb35586fSAlban Bedel- reg: Base address and size of the controllers memory area 10bb35586fSAlban Bedel- interrupts: Interrupt specifier for the controllers interrupt. 11bb35586fSAlban Bedel- interrupt-controller : Identifies the node as an interrupt controller 12bb35586fSAlban Bedel- #interrupt-cells : Specifies the number of cells needed to encode interrupt 13bb35586fSAlban Bedel source, should be 1 14bb35586fSAlban Bedel 1519446da4SAlexander CouzensCompatible fallback depends on the SoC. Use ar7100 for ar71xx and ar913x, 1619446da4SAlexander Couzensuse ar7240 for all other SoCs. 1719446da4SAlexander Couzens 18bb35586fSAlban BedelPlease refer to interrupts.txt in this directory for details of the common 19bb35586fSAlban BedelInterrupt Controllers bindings used by client devices. 20bb35586fSAlban Bedel 21bb35586fSAlban BedelExample: 22bb35586fSAlban Bedel 23bb35586fSAlban Bedel interrupt-controller@18060010 { 24*ef832242SAlban Bedel compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc"; 25bb35586fSAlban Bedel reg = <0x18060010 0x4>; 26bb35586fSAlban Bedel 27bb35586fSAlban Bedel interrupt-parent = <&cpuintc>; 28bb35586fSAlban Bedel interrupts = <6>; 29bb35586fSAlban Bedel 30bb35586fSAlban Bedel interrupt-controller; 31bb35586fSAlban Bedel #interrupt-cells = <1>; 32bb35586fSAlban Bedel }; 3319446da4SAlexander Couzens 3419446da4SAlexander CouzensAnother example: 3519446da4SAlexander Couzens 3619446da4SAlexander Couzens interrupt-controller@18060010 { 3719446da4SAlexander Couzens compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc"; 3819446da4SAlexander Couzens reg = <0x18060010 0x4>; 3919446da4SAlexander Couzens 4019446da4SAlexander Couzens interrupt-parent = <&cpuintc>; 4119446da4SAlexander Couzens interrupts = <6>; 4219446da4SAlexander Couzens 4319446da4SAlexander Couzens interrupt-controller; 4419446da4SAlexander Couzens #interrupt-cells = <1>; 4519446da4SAlexander Couzens }; 46