14c835a60SStefan Roese// SPDX-License-Identifier: GPL-2.0 24c835a60SStefan Roese 34c835a60SStefan Roese/ { 44c835a60SStefan Roese #address-cells = <1>; 54c835a60SStefan Roese #size-cells = <1>; 64c835a60SStefan Roese compatible = "ralink,mt7628a-soc"; 74c835a60SStefan Roese 84c835a60SStefan Roese cpus { 94c835a60SStefan Roese #address-cells = <1>; 104c835a60SStefan Roese #size-cells = <0>; 114c835a60SStefan Roese 124c835a60SStefan Roese cpu@0 { 134c835a60SStefan Roese compatible = "mti,mips24KEc"; 144c835a60SStefan Roese device_type = "cpu"; 154c835a60SStefan Roese reg = <0>; 164c835a60SStefan Roese }; 174c835a60SStefan Roese }; 184c835a60SStefan Roese 194c835a60SStefan Roese resetc: reset-controller { 204c835a60SStefan Roese compatible = "ralink,rt2880-reset"; 214c835a60SStefan Roese #reset-cells = <1>; 224c835a60SStefan Roese }; 234c835a60SStefan Roese 244c835a60SStefan Roese cpuintc: interrupt-controller { 254c835a60SStefan Roese #address-cells = <0>; 264c835a60SStefan Roese #interrupt-cells = <1>; 274c835a60SStefan Roese interrupt-controller; 284c835a60SStefan Roese compatible = "mti,cpu-interrupt-controller"; 294c835a60SStefan Roese }; 304c835a60SStefan Roese 314c835a60SStefan Roese palmbus@10000000 { 324c835a60SStefan Roese compatible = "palmbus", "simple-bus"; 334c835a60SStefan Roese reg = <0x10000000 0x200000>; 344c835a60SStefan Roese ranges = <0x0 0x10000000 0x1FFFFF>; 354c835a60SStefan Roese 364c835a60SStefan Roese #address-cells = <1>; 374c835a60SStefan Roese #size-cells = <1>; 384c835a60SStefan Roese 394c835a60SStefan Roese sysc: system-controller@0 { 404c835a60SStefan Roese compatible = "ralink,mt7620a-sysc", "syscon"; 414c835a60SStefan Roese reg = <0x0 0x100>; 424c835a60SStefan Roese }; 434c835a60SStefan Roese 4441f6e6ebSStefan Roese syscon-reboot { 4541f6e6ebSStefan Roese compatible = "syscon-reboot"; 4641f6e6ebSStefan Roese regmap = <&sysc>; 4741f6e6ebSStefan Roese offset = <0x34>; 4841f6e6ebSStefan Roese mask = <0x1>; 4941f6e6ebSStefan Roese }; 5041f6e6ebSStefan Roese 519a89b2b9SStefan Roese watchdog: watchdog@100 { 529a89b2b9SStefan Roese compatible = "ralink,mt7628a-wdt", "mediatek,mt7621-wdt"; 539a89b2b9SStefan Roese reg = <0x100 0x30>; 549a89b2b9SStefan Roese 559a89b2b9SStefan Roese resets = <&resetc 8>; 569a89b2b9SStefan Roese reset-names = "wdt"; 579a89b2b9SStefan Roese 589a89b2b9SStefan Roese interrupt-parent = <&intc>; 599a89b2b9SStefan Roese interrupts = <24>; 609a89b2b9SStefan Roese }; 619a89b2b9SStefan Roese 624c835a60SStefan Roese intc: interrupt-controller@200 { 634c835a60SStefan Roese compatible = "ralink,rt2880-intc"; 644c835a60SStefan Roese reg = <0x200 0x100>; 654c835a60SStefan Roese 664c835a60SStefan Roese interrupt-controller; 674c835a60SStefan Roese #interrupt-cells = <1>; 684c835a60SStefan Roese 694c835a60SStefan Roese resets = <&resetc 9>; 704c835a60SStefan Roese reset-names = "intc"; 714c835a60SStefan Roese 724c835a60SStefan Roese interrupt-parent = <&cpuintc>; 734c835a60SStefan Roese interrupts = <2>; 744c835a60SStefan Roese 754c835a60SStefan Roese ralink,intc-registers = <0x9c 0xa0 764c835a60SStefan Roese 0x6c 0xa4 774c835a60SStefan Roese 0x80 0x78>; 784c835a60SStefan Roese }; 794c835a60SStefan Roese 804c835a60SStefan Roese memory-controller@300 { 814c835a60SStefan Roese compatible = "ralink,mt7620a-memc"; 824c835a60SStefan Roese reg = <0x300 0x100>; 834c835a60SStefan Roese }; 844c835a60SStefan Roese 8560f6be12SStefan Roese gpio@600 { 8660f6be12SStefan Roese #address-cells = <1>; 8760f6be12SStefan Roese #size-cells = <0>; 8860f6be12SStefan Roese 8960f6be12SStefan Roese compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio"; 9060f6be12SStefan Roese reg = <0x600 0x100>; 9160f6be12SStefan Roese 9260f6be12SStefan Roese interrupt-parent = <&intc>; 9360f6be12SStefan Roese interrupts = <6>; 9460f6be12SStefan Roese 9560f6be12SStefan Roese gpio0: bank@0 { 9660f6be12SStefan Roese reg = <0>; 9760f6be12SStefan Roese compatible = "mtk,mt7621-gpio-bank"; 9860f6be12SStefan Roese gpio-controller; 9960f6be12SStefan Roese #gpio-cells = <2>; 10060f6be12SStefan Roese }; 10160f6be12SStefan Roese 10260f6be12SStefan Roese gpio1: bank@1 { 10360f6be12SStefan Roese reg = <1>; 10460f6be12SStefan Roese compatible = "mtk,mt7621-gpio-bank"; 10560f6be12SStefan Roese gpio-controller; 10660f6be12SStefan Roese #gpio-cells = <2>; 10760f6be12SStefan Roese }; 10860f6be12SStefan Roese 10960f6be12SStefan Roese gpio2: bank@2 { 11060f6be12SStefan Roese reg = <2>; 11160f6be12SStefan Roese compatible = "mtk,mt7621-gpio-bank"; 11260f6be12SStefan Roese gpio-controller; 11360f6be12SStefan Roese #gpio-cells = <2>; 11460f6be12SStefan Roese }; 11560f6be12SStefan Roese }; 11660f6be12SStefan Roese 1174c835a60SStefan Roese spi0: spi@b00 { 1184c835a60SStefan Roese compatible = "ralink,mt7621-spi"; 1194c835a60SStefan Roese reg = <0xb00 0x40>; 1204c835a60SStefan Roese #address-cells = <1>; 1214c835a60SStefan Roese #size-cells = <0>; 122fdd1a9ffSStefan Roese 123fdd1a9ffSStefan Roese clock-frequency = <200000000>; 1244c835a60SStefan Roese }; 1254c835a60SStefan Roese 1264c835a60SStefan Roese uart0: uartlite@c00 { 1274c835a60SStefan Roese compatible = "ns16550a"; 1284c835a60SStefan Roese reg = <0xc00 0x100>; 1294c835a60SStefan Roese 1304c835a60SStefan Roese resets = <&resetc 12>; 1314c835a60SStefan Roese reset-names = "uart0"; 1324c835a60SStefan Roese 1334c835a60SStefan Roese interrupt-parent = <&intc>; 1344c835a60SStefan Roese interrupts = <20>; 1354c835a60SStefan Roese 1364c835a60SStefan Roese reg-shift = <2>; 1374c835a60SStefan Roese }; 1384c835a60SStefan Roese 1394c835a60SStefan Roese uart1: uart1@d00 { 1404c835a60SStefan Roese compatible = "ns16550a"; 1414c835a60SStefan Roese reg = <0xd00 0x100>; 1424c835a60SStefan Roese 1434c835a60SStefan Roese resets = <&resetc 19>; 1444c835a60SStefan Roese reset-names = "uart1"; 1454c835a60SStefan Roese 1464c835a60SStefan Roese interrupt-parent = <&intc>; 1474c835a60SStefan Roese interrupts = <21>; 1484c835a60SStefan Roese 1494c835a60SStefan Roese reg-shift = <2>; 1504c835a60SStefan Roese }; 1514c835a60SStefan Roese 1524c835a60SStefan Roese uart2: uart2@e00 { 1534c835a60SStefan Roese compatible = "ns16550a"; 1544c835a60SStefan Roese reg = <0xe00 0x100>; 1554c835a60SStefan Roese 1564c835a60SStefan Roese resets = <&resetc 20>; 1574c835a60SStefan Roese reset-names = "uart2"; 1584c835a60SStefan Roese 1594c835a60SStefan Roese interrupt-parent = <&intc>; 1604c835a60SStefan Roese interrupts = <22>; 1614c835a60SStefan Roese 1624c835a60SStefan Roese reg-shift = <2>; 1634c835a60SStefan Roese }; 1644c835a60SStefan Roese }; 1654c835a60SStefan Roese 16682dbe648SStefan Roese eth@10110000 { 167*b7461e01SStefan Roese compatible = "mediatek,mt7628-eth"; 16882dbe648SStefan Roese reg = <0x10100000 0x10000 16982dbe648SStefan Roese 0x10110000 0x8000>; 17082dbe648SStefan Roese 17182dbe648SStefan Roese syscon = <&sysc>; 17282dbe648SStefan Roese }; 17382dbe648SStefan Roese 1744c835a60SStefan Roese usb_phy: usb-phy@10120000 { 1754c835a60SStefan Roese compatible = "mediatek,mt7628-usbphy"; 1764c835a60SStefan Roese reg = <0x10120000 0x1000>; 1774c835a60SStefan Roese 1784c835a60SStefan Roese #phy-cells = <0>; 1794c835a60SStefan Roese 1804c835a60SStefan Roese ralink,sysctl = <&sysc>; 1814c835a60SStefan Roese resets = <&resetc 22 &resetc 25>; 1824c835a60SStefan Roese reset-names = "host", "device"; 1834c835a60SStefan Roese }; 1844c835a60SStefan Roese 1854c835a60SStefan Roese ehci@101c0000 { 1864c835a60SStefan Roese compatible = "generic-ehci"; 1874c835a60SStefan Roese reg = <0x101c0000 0x1000>; 1884c835a60SStefan Roese 1894c835a60SStefan Roese phys = <&usb_phy>; 1904c835a60SStefan Roese phy-names = "usb"; 1914c835a60SStefan Roese 1924c835a60SStefan Roese interrupt-parent = <&intc>; 1934c835a60SStefan Roese interrupts = <18>; 1944c835a60SStefan Roese }; 1954c835a60SStefan Roese}; 196