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/openbmc/u-boot/arch/arm/dts/
H A Dsalvator-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for common parts of Salvator-X board variants
5 * Copyright (C) 2015-2016 Renesas Electronics Corp.
9 * SSI-AK4613
13 * amixer set "DVC Out" 100%
18 * amixer set "DVC Out Mute" on
23 * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
24 * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
25 * amixer set "DVC Out Ramp" on
27 * amixer set "DVC Out" 80% // Volume Down
[all …]
H A Dr8a7791-koelsch.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2013-2014 Renesas Solutions Corp.
11 * SSI-AK4643
20 * amixer set "DVC Out" 100%
25 * amixer set "DVC Out Mute" on
30 * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
31 * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
32 * amixer set "DVC Out Ramp" on
34 * amixer set "DVC Out" 80% // Volume Down
35 * amixer set "DVC Out" 100% // Volume Up
[all …]
H A Dr8a7790-lager.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
7 * Copyright (C) 2015-2016 Renesas Electronics Corporation
11 * SSI-AK4643
20 * amixer set "DVC Out" 100%
25 * amixer set "DVC Out Mute" on
30 * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
31 * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
32 * amixer set "DVC Out Ramp" on
34 * amixer set "DVC Out" 80% // Volume Down
[all …]
H A Dr8a7793-gose.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2015 Renesas Electronics Corporation
9 * SSI-AK4643
18 * amixer set "DVC Out" 100%
23 * amixer set "DVC Out Mute" on
28 * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
29 * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
30 * amixer set "DVC Out Ramp" on
32 * amixer set "DVC Out" 80% // Volume Down
33 * amixer set "DVC Out" 100% // Volume Up
[all …]
H A Dstm32h743.dtsi2 * Copyright 2017 - Alexandre Torgue <alexandre.torgue@st.com>
4 * This file is dual-licensed: you can use it either under the terms
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
44 #include "armv7-m.dtsi"
45 #include <dt-bindings/clock/stm32h7-clks.h>
46 #include <dt-bindings/mfd/stm32h7-rcc.h>
50 clk_hse: clk-hse {
51 #clock-cells = <0>;
52 compatible = "fixed-clock";
53 clock-frequency = <25000000>;
[all …]
/openbmc/linux/arch/arm64/boot/dts/renesas/
H A Dsalvator-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for common parts of Salvator-X board variants
5 * Copyright (C) 2015-2016 Renesas Electronics Corp.
9 * SSI-AK4613
13 * amixer set "DVC Out" 100%
18 * amixer set "DVC Out Mute" on
23 * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
24 * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
25 * amixer set "DVC Out Ramp" on
27 * amixer set "DVC Out" 80% // Volume Down
[all …]
/openbmc/linux/arch/powerpc/boot/dts/
H A Dkmeter1.dts1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * 2008-2011 DENX Software Engineering GmbH
8 /dts-v1/;
13 #address-cells = <1>;
14 #size-cells = <1>;
28 #address-cells = <1>;
29 #size-cells = <0>;
34 d-cache-line-size = <32>; // 32 bytes
35 i-cache-line-size = <32>; // 32 bytes
36 d-cache-size = <32768>; // L1, 32K
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dqca,ar803x.yaml1 # SPDX-License-Identifier: GPL-2.0+
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <andrew@lunn.ch>
11 - Florian Fainelli <f.fainelli@gmail.com>
12 - Heiner Kallweit <hkallweit1@gmail.com>
18 - $ref: ethernet-phy.yaml#
21 qca,clk-out-frequency:
22 description: Clock output frequency in Hertz.
26 qca,clk-out-strength:
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dsilabs,si5341.txt2 i2c clock generator.
6 https://www.silabs.com/documents/public/data-sheets/Si5341-40-D-DataSheet.pdf
8 https://www.silabs.com/documents/public/reference-manuals/Si5341-40-D-RM.pdf
10 https://www.silabs.com/documents/public/reference-manuals/Si5345-44-42-D-RM.pdf
12 The Si5341 and Si5340 are programmable i2c clock generators with up to 10 output
15 The internal structure of the clock generators can be found in [2].
21 chip at boot, in case you have a (pre-)programmed device. If the PLL is not
33 - compatible: shall be one of the following:
34 "silabs,si5340" - Si5340 A/B/C/D
35 "silabs,si5341" - Si5341 A/B/C/D
[all …]
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_gt_clock_utils.c1 // SPDX-License-Identifier: MIT
62 * Note that on gen11+, the clock frequency may be reconfigured. in gen11_read_clock_frequency()
65 * First figure out the reference frequency. There are 2 ways in gen11_read_clock_frequency()
66 * we can compute the frequency, either through the in gen11_read_clock_frequency()
78 * Now figure out how the command stream's timestamp in gen11_read_clock_frequency()
79 * register increments from this frequency (it might in gen11_read_clock_frequency()
80 * increment only every few clock cycle). in gen11_read_clock_frequency()
82 freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >> in gen11_read_clock_frequency()
97 freq = IS_GEN9_LP(uncore->i915) ? 19200000 : 24000000; in gen9_read_clock_frequency()
100 * Now figure out how the command stream's timestamp in gen9_read_clock_frequency()
[all …]
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Dr8a7791-koelsch.dts1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (C) 2013-2014 Renesas Solutions Corp.
11 * SSI-AK4643
20 * amixer set "DVC Out" 100%
25 * amixer set "DVC Out Mute" on
30 * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
31 * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
32 * amixer set "DVC Out Ramp" on
34 * amixer set "DVC Out" 80% // Volume Down
35 * amixer set "DVC Out" 100% // Volume Up
[all …]
H A Dr8a7790-lager.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2013-2014 Renesas Solutions Corp.
7 * Copyright (C) 2015-2016 Renesas Electronics Corporation
11 * SSI-AK4643
20 * amixer set "DVC Out" 100%
25 * amixer set "DVC Out Mute" on
30 * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
31 * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
32 * amixer set "DVC Out Ramp" on
34 * amixer set "DVC Out" 80% // Volume Down
[all …]
H A Dr8a7793-gose.dts1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2014-2015 Renesas Electronics Corporation
9 * SSI-AK4643
18 * amixer set "DVC Out" 100%
23 * amixer set "DVC Out Mute" on
28 * amixer set "DVC Out Ramp Up Rate" "0.125 dB/64 steps"
29 * amixer set "DVC Out Ramp Down Rate" "0.125 dB/512 steps"
30 * amixer set "DVC Out Ramp" on
32 * amixer set "DVC Out" 80% // Volume Down
33 * amixer set "DVC Out" 100% // Volume Up
[all …]
/openbmc/u-boot/drivers/clk/sifive/
H A Dwrpll-cln28hpc.c1 // SPDX-License-Identifier: GPL-2.0
24 * The bulk of this code is primarily useful for clock configurations
25 * that must operate at arbitrary rates, as opposed to clock configurations
27 * pre-determined set of performance points.
30 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
31 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
39 #include "analogbits-wrpll-cln28hpc.h"
41 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
44 /* MAX_INPUT_FREQ: maximum input clock frequency, in Hz (Fref_max) */
47 /* MIN_POST_DIVIDE_REF_FREQ: minimum post-divider reference frequency, in Hz */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/net/can/
H A Dcc770.txt8 - compatible : should be "bosch,cc770" for the CC770 and "intc,82527"
11 - reg : should specify the chip select, address offset and size required
14 - interrupts : property with a value describing the interrupt source
19 - bosch,external-clock-frequency : frequency of the external oscillator
20 clock in Hz. Note that the internal clock frequency used by the
24 - bosch,clock-out-frequency : slock frequency in Hz on the CLKOUT pin.
28 - bosch,slew-rate : slew rate of the CLKOUT signal. If not specified,
31 - bosch,disconnect-rx0-input : see data sheet.
33 - bosch,disconnect-rx1-input : see data sheet.
35 - bosch,disconnect-tx1-output : see data sheet.
[all …]
H A Dnxp,sja1000.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Wolfgang Grandegger <wg@grandegger.com>
15 - enum:
16 - nxp,sja1000
17 - technologic,sja1000
18 - items:
19 - enum:
20 - renesas,r9a06g032-sja1000 # RZ/N1D
[all …]
/openbmc/linux/drivers/clk/analogbits/
H A Dwrpll-cln28hpc.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2018-2019 SiFive, Inc.
13 * The bulk of this code is primarily useful for clock configurations
14 * that must operate at arbitrary rates, as opposed to clock configurations
16 * pre-determined set of performance points.
19 * - Analog Bits "Wide Range PLL Datasheet", version 2015.10.01
20 * - SiFive FU540-C000 Manual v1p0, Chapter 7 "Clocking and Reset"
21 * https://static.dev.sifive.com/FU540-C000-v1.0.pdf
32 #include <linux/clk/analogbits-wrpll-cln28hpc.h>
34 /* MIN_INPUT_FREQ: minimum input clock frequency, in Hz (Fref_min) */
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-tegra/
H A Dclock.h1 /* SPDX-License-Identifier: GPL-2.0+ */
6 /* Tegra clock control functions */
25 * Note that no Tegra clock register actually uses all of bits 31:28 as
29 * register. As such, the U-Boot clock driver is currently a bit lazy, and
39 #include <asm/arch/clock-tables.h>
43 /* return the current oscillator clock frequency */
46 /* return the clk_m frequency */
52 * @param id clock id
65 * Set PLL output frequency
67 * @param clkid clock id
[all …]
/openbmc/linux/Documentation/driver-api/media/
H A Dcamera-sensor.rst1 .. SPDX-License-Identifier: GPL-2.0
6 CSI-2 and parallel (BT.601 and BT.656) busses
7 ---------------------------------------------
9 Please see :ref:`transmitter-receiver`.
12 ---------------
14 Camera sensors have an internal clock tree including a PLL and a number of
15 divisors. The clock tree is generally configured by the driver based on a few
16 input parameters that are specific to the hardware:: the external clock frequency
17 and the link frequency. The two parameters generally are obtained from system
20 The reason why the clock frequencies are so important is that the clock signals
[all …]
/openbmc/linux/Documentation/devicetree/bindings/iio/frequency/
H A Dadi,adrf6780.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/iio/frequency/adi,adrf6780.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Antoniu Miclaus <antoniu.miclaus@analog.com>
14 radio designs operating in the 5.9 GHz to 23.6 GHz frequency range.
21 - adi,adrf6780
26 spi-max-frequency:
31 Definition of the external clock.
34 clock-names:
[all …]
/openbmc/linux/Documentation/timers/
H A Dtimekeeping.rst2 Clock sources, Clock events, sched_clock() and delay timers
7 drivers/clocksource in the kernel tree, but the code may be spread out
10 If you grep through the kernel source you will find a number of architecture-
11 specific implementations of clock sources, clockevents and several likewise
12 architecture-specific overrides of the sched_clock() function and some
15 To provide timekeeping for your platform, the clock source provides
16 the basic timeline, whereas clock events shoot interrupts on certain points
17 on this timeline, providing facilities such as high-resolution timers.
22 Clock sources
23 -------------
[all …]
/openbmc/linux/sound/aoa/soundbus/i2sbus/
H A Dinterface.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * i2sbus driver -- interface register definitions
61 * - clock source
62 * - MClk divisor
63 * - SClk divisor
64 * - SClk master flag
65 * - serial format (sony, i2s 64x, i2s 32x, dav, silabs)
66 * - external sample frequency interrupt (don't understand)
67 * - external sample frequency
70 /* clock source. You get either 18.432, 45.1584 or 49.1520 MHz */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dsimple-card.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/sound/simple-card.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
14 frame-master:
15 description: Indicates dai-link frame master.
18 bitclock-master:
19 description: Indicates dai-link bit clock master
22 frame-inversion:
[all …]
/openbmc/linux/Documentation/virt/hyperv/
H A Dclocks.rst1 .. SPDX-License-Identifier: GPL-2.0
7 -----
8 On arm64, Hyper-V virtualizes the ARMv8 architectural system counter
12 architectural system counter is functional in guest VMs on Hyper-V.
13 While Hyper-V also provides a synthetic system clock and four synthetic
14 per-CPU timers as described in the TLFS, they are not used by the
15 Linux kernel in a Hyper-V guest on arm64. However, older versions
16 of Hyper-V for arm64 only partially virtualize the ARMv8
19 Linux kernel versions on these older Hyper-V versions requires an
20 out-of-tree patch to use the Hyper-V synthetic clocks/timers instead.
[all …]
/openbmc/linux/drivers/cpufreq/
H A Dpasemi-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-or-later
48 /* We support 5(A0-A4) power states excluding turbo(A5-A6) modes */
132 int err = -ENODEV; in pas_cpufreq_cpu_init()
134 cpu = of_get_cpu_node(policy->cpu, NULL); in pas_cpufreq_cpu_init()
136 goto out; in pas_cpufreq_cpu_init()
138 max_freqp = of_get_property(cpu, "clock-frequency", NULL); in pas_cpufreq_cpu_init()
141 err = -EINVAL; in pas_cpufreq_cpu_init()
142 goto out; in pas_cpufreq_cpu_init()
148 dn = of_find_compatible_node(NULL, NULL, "1682m-sdc"); in pas_cpufreq_cpu_init()
151 "pasemi,pwrficient-sdc"); in pas_cpufreq_cpu_init()
[all …]

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