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/openbmc/linux/drivers/media/rc/
H A Drc-core-priv.h1 /* SPDX-License-Identifier: GPL-2.0 */
17 #include <media/rc-core.h>
20 * rc_open - Opens a RC device
27 * rc_close - Closes a RC device
169 return d1 > (d2 - margin); in geq_margin()
174 return ((d1 > (d2 - margin)) && (d1 < (d2 + margin))); in eq_margin()
179 return x->pulse != y->pulse; in is_transition()
182 static inline void decrease_duration(struct ir_raw_event *ev, unsigned duration) in decrease_duration() argument
184 if (duration > ev->duration) in decrease_duration()
185 ev->duration = 0; in decrease_duration()
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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dst,stm32-fmc2-ebi-props.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi-props.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Christophe Kerello <christophe.kerello@foss.st.com>
11 - Marek Vasut <marex@denx.de>
14 st,fmc2-ebi-cs-transaction-type:
33 st,fmc2-ebi-cs-cclk-enable:
34 description: Continuous clock enable (first bank must be configured
40 st,fmc2-ebi-cs-mux-enable:
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/openbmc/qemu/include/hw/
H A Dclock.h4 * Copyright GreenSocs 2016-2020
11 * See the COPYING file in the top-level directory.
19 #include "qemu/host-utils.h"
22 #define TYPE_CLOCK "clock"
23 OBJECT_DECLARE_SIMPLE_TYPE(Clock, CLOCK)
32 ClockUpdate = 1, /* Clock period has just updated */
33 ClockPreUpdate = 2, /* Clock period is about to update */
39 * clock store a value representing the clock's period in 2^-32ns unit.
41 * + periods from 2^-32ns up to 4seconds
53 #define CLOCK_PERIOD_FROM_NS(ns) ((ns) * (CLOCK_PERIOD_1SEC / 1000000000llu)) argument
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/openbmc/linux/Documentation/devicetree/bindings/gpio/
H A Dgpio-latch.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/gpio/gpio-latch.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sascha Hauer <s.hauer@pengutronix.de>
16 CLK0 ----------------------. ,--------.
17 CLK1 -------------------. `--------|> #0 |
19 OUT0 ----------------+--|-----------|D0 Q0|-----|<
20 OUT1 --------------+-|--|-----------|D1 Q1|-----|<
21 OUT2 ------------+-|-|--|-----------|D2 Q2|-----|<
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/openbmc/linux/Documentation/trace/
H A Dtimerlat-tracer.rst6 find sources of wakeup latencies of real-time threads. Like cyclictest,
13 -----
28 # _-----=> irqs-off
29 # / _----=> need-resched
30 # | / _---=> hardirq/softirq
31 # || / _--=> preempt-depth
34 # TASK-PID CPU# |||| TIMESTAMP ID CONTEXT LATENCY
36 <idle>-0 [000] d.h1 54.029328: #1 context irq timer_latency 932 ns
37 <...>-867 [000] .... 54.029339: #1 context thread timer_latency 11700 ns
38 <idle>-0 [001] dNh1 54.029346: #1 context irq timer_latency 2833 ns
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/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Domap3-n950-n9.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
3 * omap3-n950-n9.dtsi - Device Tree file for Nokia N950 & N9 (common stuff)
13 cpu0-supply = <&vcc>;
23 compatible = "regulator-fixed";
24 regulator-name = "VEMMC";
25 regulator-min-microvolt = <2900000>;
26 regulator-max-microvolt = <2900000>;
28 startup-delay-us = <150>;
29 enable-active-high;
33 compatible = "regulator-fixed";
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/openbmc/linux/drivers/gpio/
H A Dgpio-latch.c1 // SPDX-License-Identifier: GPL-2.0
10 * CLK0 ----------------------. ,--------.
11 * CLK1 -------------------. `--------|> #0 |
13 * OUT0 ----------------+--|-----------|D0 Q0|-----|<
14 * OUT1 --------------+-|--|-----------|D1 Q1|-----|<
15 * OUT2 ------------+-|-|--|-----------|D2 Q2|-----|<
16 * OUT3 ----------+-|-|-|--|-----------|D3 Q3|-----|<
17 * OUT4 --------+-|-|-|-|--|-----------|D4 Q4|-----|<
18 * OUT5 ------+-|-|-|-|-|--|-----------|D5 Q5|-----|<
19 * OUT6 ----+-|-|-|-|-|-|--|-----------|D6 Q6|-----|<
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/openbmc/linux/kernel/time/
H A Dsched_clock.c1 // SPDX-License-Identifier: GPL-2.0
4 * counters to full 64-bit ns values.
14 #include <linux/sched/clock.h>
24 * struct clock_data - all data needed for sched_clock() (including
25 * registration of a new clock source)
30 * @wrap_kt: Duration for which clock can run before wrapping.
31 * @rate: Tick rate of the registered clock.
32 * @actual_read_sched_clock: Registered hardware level clock read function.
36 * into a single 64-byte cache line.
48 static int irqtime = -1;
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H A Dntp.c1 // SPDX-License-Identifier: GPL-2.0
49 * phase-lock loop variables
53 * clock synchronization status
55 * (TIME_ERROR prevents overwriting the CMOS clock)
59 /* clock status bits: */
82 /* constant (boot-param configurable) NTP tick adjustment (upscaled) */
91 * The following variables are used when a pulse-per-second (PPS) signal
92 * is available. They establish the engineering parameters of the clock
102 #define PPS_MAXWANDER 100000 /* max PPS freq wander (ns/s) */
106 static long pps_jitter; /* current jitter (ns) */
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/openbmc/u-boot/drivers/i2c/
H A Dmvtwsi.c1 // SPDX-License-Identifier: GPL-2.0+
87 /* Number of the device (determined from cell-index property) */
93 /* The current length of a clock period (depending on speed) */
99 * enum mvtwsi_ctrl_register_fields - Bit masks for flags in the control
118 * On sun6i and newer, IFLG is a write-clear bit, which is cleared by writing 1;
129 * enum mvstwsi_status_values - Possible values of I2C controller's status
133 * non-10-bit-address devices are specified.
161 * enum mvstwsi_ack_flags - Determine whether a read byte should be
172 * calc_tick() - Calculate the duration of a clock cycle from the I2C speed
174 * @speed: The speed in Hz to calculate the clock cycle duration for.
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/openbmc/linux/drivers/media/i2c/cx25840/
H A Dcx25840-ir.c1 // SPDX-License-Identifier: GPL-2.0-or-later
13 #include <media/drv-intf/cx25840.h>
14 #include <media/rc-core.h>
16 #include "cx25840-core.h"
117 return state ? state->ir_state : NULL; in to_ir_state()
122 * Rx and Tx Clock Divider register computations
124 * Note the largest clock divider value of 0xffff corresponds to:
125 * (0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns
135 d--; in count_to_clock_divider()
161 * 0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns
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/openbmc/linux/drivers/media/pci/cx23885/
H A Dcx23888-ir.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include "cx23888-ir.h"
16 #include <media/v4l2-device.h>
17 #include <media/rc-core.h>
161 * Rx and Tx Clock Divider register computations
163 * Note the largest clock divider value of 0xffff corresponds to:
164 * (0xffff + 1) * 1000 / 108/2 MHz = 1,213,629.629... ns
174 d--; in count_to_clock_divider()
200 * 0xffff * 1000 / 108/2 MHz = 1,213,611.11... ns
212 static inline u16 ns_to_lpf_count(unsigned int ns) in ns_to_lpf_count() argument
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/openbmc/bmcweb/redfish-core/schema/dmtf/csdl/
H A DProcessorMetrics_v1.xml1 <?xml version="1.0" encoding="UTF-8"?>
2 <!---->
3 <!--################################################################################ -->
4 <!--# Redfish Schema: ProcessorMetrics v1.6.4 -->
5 <!--# -->
6 <!--# For a detailed change log, see the README file contained in the DSP8010 bundle, -->
7 <!--# available at http://www.dmtf.org/standards/redfish -->
8 <!--# Copyright 2014-2024 DMTF. -->
9 <!--# For the full DMTF copyright policy, see http://www.dmtf.org/about/policies/copyright -->
10 <!--################################################################################ -->
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/openbmc/linux/drivers/cpufreq/
H A Dsa1110-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * linux/arch/arm/mach-sa1100/cpu-sa1110.c
8 * 7 - SDRAM auto-power-up failure (rev A0)
9 * 13 - Corruption of internal register reads/writes following
25 #include <asm/mach-types.h>
36 u_char tck; /* clock cycle time (ns) */
37 u_char trcd; /* activate to r/w (ns) */
38 u_char trp; /* precharge to activate (ns) */
39 u_char twr; /* write recovery time (ns) */
51 .name = "TC59SM716-CL2",
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/openbmc/linux/include/uapi/linux/
H A Dtimex.h28 * Added defines for hybrid phase/frequency-lock loop.
32 * defines for PPS phase-lock loop.
35 * Revised status codes and structures for external clock and PPS
46 * 1995-08-13 Torsten Duwe
47 * kernel PLL updated to 1994-12-13 specs (rfc-1589)
48 * 1997-08-30 Ulrich Windl
50 * 2004-08-12 Christoph Lameter
62 * syscall interface - used (mainly by NTP daemon)
63 * to discipline kernel clock oscillator
71 int status; /* clock command/status */
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/openbmc/linux/drivers/net/fddi/skfp/
H A Dhwt.c1 // SPDX-License-Identifier: GPL-2.0-or-later
20 * 28-Jun-1994 sw Edit v1.6.
21 * MCA: Added support for the SK-NET FDDI-FM2 adapter. The
33 /* 28-Jun-1994 sw - Note: hwt_restart() is also used in module 'drvfbi.c'. */
40 * Start hardware timer (clock ticks are 16us).
46 * smc - A pointer to the SMT Context structure.
48 * time - The time in units of 16us to load the timer with.
62 smc->hw.t_start = time ; in hwt_start()
63 smc->hw.t_stop = 0L ; in hwt_start()
76 smc->hw.timer_activ = TRUE ; in hwt_start()
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/openbmc/qemu/docs/devel/
H A Dclocks.rst1 Modelling a clock tree in QEMU
5 ----------------
10 They allow us to model the clock distribution of a platform and detect
11 configuration errors in the clock tree such as badly configured PLL, clock
12 source selection or disabled clock.
14 The object is *Clock* and its QOM name is ``clock`` (in C code, the macro
21 In these cases a Clock object is a child of a Device object, but this
23 example it is possible to create a clock outside of any device to
24 model the main clock source of a machine.
28 +---------+ +----------------------+ +--------------+
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/openbmc/linux/drivers/net/ethernet/mellanox/mlx5/core/lib/
H A Dclock.c14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
37 #include <rdma/mlx5-abi.h>
40 #include "clock.h"
72 MLX5_MTUTC_OPERATION_ADJUST_TIME_EXTENDED_MIN = -200000,
107 * dev_freq_khz = 2^(shift_constant - 16) in mlx5_ptp_shift_constant()
120 struct mlx5_clock *clock = container_of(ptp, struct mlx5_clock, ptp_info); in mlx5_ptp_getmaxphase() local
123 mdev = container_of(clock, struct mlx5_core_dev, clock); in mlx5_ptp_getmaxphase()
132 s64 max = mlx5_ptp_getmaxphase(&mdev->clock.ptp_info); in mlx5_is_mtutc_time_adj_cap()
134 if (delta < -max || delta > max) in mlx5_is_mtutc_time_adj_cap()
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/openbmc/linux/tools/tracing/rtla/src/
H A Dtimerlat_aa.c1 // SPDX-License-Identifier: GPL-2.0
25 * Per-cpu data statistics and data.
66 * If now - timestamp is <= latency, it might have influenced
137 * timerlat_aa_get_data - Get the per-cpu data from the timerlat context
142 return &taa_ctx->taa_data[cpu]; in timerlat_aa_get_data()
146 * timerlat_aa_irq_latency - Handles timerlat IRQ event
156 taa_data->curr_state = TIMERLAT_WAITING_THREAD; in timerlat_aa_irq_latency()
157 taa_data->tlat_irq_timstamp = record->ts; in timerlat_aa_irq_latency()
162 taa_data->thread_nmi_sum = 0; in timerlat_aa_irq_latency()
163 taa_data->thread_irq_sum = 0; in timerlat_aa_irq_latency()
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/openbmc/u-boot/arch/arm/mach-kirkwood/
H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0+
5 * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
21 writel(readl(&cpureg->rstoutn_mask) | (1 << 2), in reset_cpu()
22 &cpureg->rstoutn_mask); in reset_cpu()
23 writel(readl(&cpureg->sys_soft_rst) | 1, in reset_cpu()
24 &cpureg->sys_soft_rst); in reset_cpu()
34 * NOTE: A value of 0x0 specifies 64-KByte size.
50 * kw_config_adr_windows - Configure address Windows
59 * Mbus-L to Mbus Bridge Registers Configuration.
106 /* Window 6-7: Disabled */ in kw_config_adr_windows()
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/openbmc/linux/tools/include/uapi/sound/
H A Dasound.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
3 * Advanced Linux Sound Architecture - ALSA - Driver
4 * Copyright (c) 1994-2003 by Jaroslav Kysela <perex@perex.cz>,
5 * Abramo Bagnara <abramo@alsa-project.org>
54 * CEA-861 Audio InfoFrame. Used in HDMI and DisplayPort *
63 unsigned char db5_dminh_lsv; /* downmix inhibit & level-shit values */
68 * Section for driver hardware dependent interface - /dev/snd/hw? *
91 SNDRV_HWDEP_IFACE_HDA, /* HD-audio */
118 unsigned int version; /* R: driver-specific version */
119 unsigned char id[32]; /* R: driver-specific ID string */
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/openbmc/linux/include/uapi/sound/
H A Dasound.h1 /* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
3 * Advanced Linux Sound Architecture - ALSA - Driver
4 * Copyright (c) 1994-2003 by Jaroslav Kysela <perex@perex.cz>,
5 * Abramo Bagnara <abramo@alsa-project.org>
54 * CEA-861 Audio InfoFrame. Used in HDMI and DisplayPort *
63 unsigned char db5_dminh_lsv; /* downmix inhibit & level-shit values */
68 * Section for driver hardware dependent interface - /dev/snd/hw? *
91 SNDRV_HWDEP_IFACE_HDA, /* HD-audio */
118 unsigned int version; /* R: driver-specific version */
119 unsigned char id[32]; /* R: driver-specific ID string */
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/openbmc/linux/Documentation/devicetree/bindings/opp/
H A Dopp-v2-base.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/opp/opp-v2-base.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Viresh Kumar <viresh.kumar@linaro.org>
13 Devices work at voltage-current-frequency combinations and some implementations
25 pattern: '^opp-table(-[a-z0-9]+)?$'
27 opp-shared:
30 their DVFS state together, i.e. they share clock/voltage/current lines.
31 Missing property means devices have independent clock/voltage/current
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/openbmc/linux/drivers/net/dsa/sja1105/
H A Dsja1105_tas.c1 // SPDX-License-Identifier: GPL-2.0
10 #define SJA1105_GATE_MASK GENMASK_ULL(SJA1105_NUM_TC - 1, 0)
19 struct sja1105_tas_data *tas_data = &priv->tas_data; in sja1105_tas_set_runtime_params()
20 struct sja1105_gating_config *gating_cfg = &tas_data->gating_cfg; in sja1105_tas_set_runtime_params()
21 struct dsa_switch *ds = priv->ds; in sja1105_tas_set_runtime_params()
28 tas_data->enabled = false; in sja1105_tas_set_runtime_params()
30 for (port = 0; port < ds->num_ports; port++) { in sja1105_tas_set_runtime_params()
33 offload = tas_data->offload[port]; in sja1105_tas_set_runtime_params()
37 tas_data->enabled = true; in sja1105_tas_set_runtime_params()
39 if (max_cycle_time < offload->cycle_time) in sja1105_tas_set_runtime_params()
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/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c1 // SPDX-License-Identifier: GPL-2.0+
5 * (C) Copyright 2007-2015
10 * Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
18 #include <asm/arch/clock.h>
26 * Allwinner as part of the open-source bootloader release (refer to
27 * https://github.com/allwinner-zh/bootloader.git) and augments the upstream
36 * Note that the Zynq-documentation provides a very close match for the DDR
42 * (i.e. the rules for MEMC_FREQ_RATIO=2 from the Zynq-documentation apply).
48 * 1) Only DDR3 support is implemented, as our test platform (the A80-Q7
50 * 2) Only 2T-mode has been implemented and tested.
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