/openbmc/linux/drivers/media/platform/qcom/camss/ |
H A D | camss-vfe.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * camss-vfe.c 5 * Qualcomm MSM Camera Subsystem - VFE (Video Front End) Module 7 * Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. 8 * Copyright (C) 2015-2018 Linaro Ltd. 10 #include <linux/clk.h> 20 #include <media/media-entity.h> 21 #include <media/v4l2-device.h> 22 #include <media/v4l2-subdev.h> 24 #include "camss-vfe.h" [all …]
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/openbmc/qemu/include/hw/misc/ |
H A D | npcm7xx_clk.h | 29 #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in" 31 /* Maximum amount of clock inputs in a SEL module. */ 34 /* PLLs in CLK module. */ 43 /* SEL/MUX in CLK module. */ 57 /* Dividers in CLK module. */ 86 * struct NPCM7xxClockPLLState - A PLL module in CLK module. 88 * @clk: The CLK module that owns this module. 90 * @clock_out: The output clock of this module. 97 NPCM7xxCLKState *clk; member 105 * struct NPCM7xxClockSELState - A SEL module in CLK module. [all …]
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/openbmc/u-boot/doc/device-tree-bindings/net/ |
H A D | ti,dp83867.txt | 1 * Texas Instruments - dp83867 Giga bit ethernet phy 4 - reg - The ID number for the phy, usually a small integer 5 - ti,rx-internal-delay - RGMII Recieve Clock Delay - see dt-bindings/net/ti-dp83867.h 7 - ti,tx-internal-delay - RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h 9 - ti,fifo-depth - Transmitt FIFO depth- see dt-bindings/net/ti-dp83867.h 11 - enet-phy-lane-swap - Indicates that PHY will swap the TX/RX lanes to 13 - enet-phy-no-lane-swap - Indicates that PHY will disable swap of the 15 - ti,clk-output-sel - Clock output select - see dt-bindings/net/ti-dp83867.h 23 ethernet-phy@0 { 25 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; [all …]
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/openbmc/linux/drivers/i2c/busses/ |
H A D | i2c-cbus-gpio.c | 4 * Copyright (C) 2004-2010 Nokia Corporation 40 struct gpio_desc *clk; member 42 struct gpio_desc *sel; member 46 * cbus_send_bit - sends one bit over the bus 52 gpiod_set_value(host->dat, bit ? 1 : 0); in cbus_send_bit() 53 gpiod_set_value(host->clk, 1); in cbus_send_bit() 54 gpiod_set_value(host->clk, 0); in cbus_send_bit() 58 * cbus_send_data - sends @len amount of data over the bus 67 for (i = len; i > 0; i--) in cbus_send_data() 68 cbus_send_bit(host, data & (1 << (i - 1))); in cbus_send_data() [all …]
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/openbmc/linux/drivers/media/i2c/ |
H A D | tw9910.c | 1 // SPDX-License-Identifier: GPL-2.0 13 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> 18 #include <linux/clk.h> 26 #include <linux/v4l2-mediabus.h> 30 #include <media/v4l2-subdev.h> 41 #define OPFORM 0x03 /* Output Format Control Register */ 43 #define OUTCTR1 0x05 /* Output Control I */ 64 #define OUTCTR2 0x1B /* Output Control 2 */ 136 #define IFSEL_S 0x10 /* 01 : S-video decoding */ 146 /* 1 : ITU-R-656 compatible data sequence format */ [all …]
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H A D | mt9v032.c | 1 // SPDX-License-Identifier: GPL-2.0-only 12 #include <linux/clk.h> 23 #include <linux/v4l2-mediabus.h> 27 #include <media/v4l2-ctrls.h> 28 #include <media/v4l2-device.h> 29 #include <media/v4l2-fwnode.h> 30 #include <media/v4l2-subdev.h> 203 struct clk *clk; member 228 struct regmap *map = mt9v032->regmap; in mt9v032_update_aec_agc() 229 u16 value = mt9v032->aec_agc; in mt9v032_update_aec_agc() [all …]
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H A D | mt9t112.c | 1 // SPDX-License-Identifier: GPL-2.0 14 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> 20 * v4l-utils compliance tools will report errors. 23 #include <linux/clk.h> 30 #include <linux/v4l2-mediabus.h> 34 #include <media/v4l2-common.h> 35 #include <media/v4l2-image-sizes.h> 36 #include <media/v4l2-subdev.h> 95 struct clk *clk; member 158 msg[0].addr = client->addr; in __mt9t112_reg_read() [all …]
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H A D | imx296.c | 1 // SPDX-License-Identifier: GPL-2.0 8 #include <linux/clk.h> 19 #include <media/v4l2-ctrls.h> 20 #include <media/v4l2-fwnode.h> 21 #include <media/v4l2-subdev.h> 196 struct clk *clk; member 224 ret = regmap_raw_read(sensor->regmap, addr & IMX296_REG_ADDR_MASK, data, in imx296_read() 240 ret = regmap_raw_write(sensor->regmap, addr & IMX296_REG_ADDR_MASK, in imx296_write() 243 dev_err(sensor->dev, "%u-bit write to 0x%04x failed: %d\n", in imx296_write() 257 ret = regulator_bulk_enable(ARRAY_SIZE(sensor->supplies), in imx296_power_on() [all …]
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H A D | mt9p031.c | 1 // SPDX-License-Identifier: GPL-2.0-only 6 * Copyright (C) 2011, Javier Martin <javier.martin@vista-silicon.com> 12 #include <linux/clk.h> 27 #include <media/v4l2-async.h> 28 #include <media/v4l2-ctrls.h> 29 #include <media/v4l2-device.h> 30 #include <media/v4l2-fwnode.h> 31 #include <media/v4l2-subdev.h> 33 #include "aptina-pll.h" 129 struct clk *clk; member [all …]
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H A D | rj54n1cb0c.c | 1 // SPDX-License-Identifier: GPL-2.0 10 #include <linux/clk.h> 16 #include <linux/v4l2-mediabus.h> 20 #include <media/v4l2-device.h> 21 #include <media/v4l2-ctrls.h> 22 #include <media/v4l2-subdev.h> 154 struct clk *clk; member 162 unsigned short width; /* Output window */ 164 unsigned short resize; /* Sensor * 1024 / resize = Output */ 416 /* Clock dividers - these are default register values, divider = register + 1 */ [all …]
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H A D | ov6650.c | 1 // SPDX-License-Identifier: GPL-2.0-only 15 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net> 25 #include <linux/clk.h> 29 #include <linux/v4l2-mediabus.h> 32 #include <media/v4l2-ctrls.h> 33 #include <media/v4l2-device.h> 36 #define REG_GAIN 0x00 /* range 00 - 3F */ 51 /* [5:0]: Internal Clock Pre-Scaler */ 165 #define W_QCIF (DEF_HSTOP - DEF_HSTRT) 167 #define H_QCIF (DEF_VSTOP - DEF_VSTRT) [all …]
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/openbmc/linux/sound/soc/sh/rcar/ |
H A D | adg.c | 1 // SPDX-License-Identifier: GPL-2.0 3 // Helper routines for R-Car sound ADG. 6 #include <linux/clk-provider.h> 33 struct clk *clkin[CLKINMAX]; 34 struct clk *clkout[CLKOUTMAX]; 35 struct clk *null_clk; 50 (i < adg->clkin_size) && \ 51 ((pos) = adg->clkin[i]); \ 55 (i < adg->clkout_size) && \ 56 ((pos) = adg->clkout[i]); \ [all …]
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/openbmc/u-boot/drivers/clk/ |
H A D | clk_stm32mp1.c | 1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause 3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved 7 #include <clk-uclass.h> 15 #include <dt-bindings/clock/stm32mp1-clks.h> 16 #include <dt-bindings/clock/stm32mp1-clksrc.h> 380 u8 sel; member 406 const struct stm32mp1_clk_sel *sel; member 424 .sel = (s), \ 434 .sel = _UNKNOWN_SEL, \ 444 .sel = (s), \ [all …]
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/openbmc/linux/Documentation/devicetree/bindings/net/ |
H A D | ti,dp83869.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) 4 --- 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - $ref: ethernet-phy.yaml# 14 - Andrew Davis <afd@ti.com> 17 The DP83869HM device is a robust, fully-featured Gigabit (PHY) transceiver 18 with integrated PMD sublayers that supports 10BASE-Te, 100BASE-TX and 19 1000BASE-T Ethernet protocols. The DP83869 also supports 1000BASE-X and 20 100BASE-FX Fiber protocols. 23 the DP83869HM can run 1000BASE-X-to-1000BASE-T and 100BASE-FX-to-100BASE-TX [all …]
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H A D | ti,dp83867.yaml | 1 # SPDX-License-Identifier: (GPL-2.0+ OR BSD-2-Clause) 4 --- 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - $ref: ethernet-controller.yaml# 14 - Andrew Davis <afd@ti.com> 18 transceiver with integrated PMD sublayers to support 10BASE-Te, 100BASE-TX 19 and 1000BASE-T Ethernet protocols. 34 nvmem-cells: 40 nvmem-cell-names: 42 - const: io_impedance_ctrl [all …]
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/openbmc/u-boot/arch/arm/mach-exynos/ |
H A D | clock.c | 1 // SPDX-License-Identifier: GPL-2.0+ 10 #include <asm/arch/clk.h> 32 {PERIPH_ID_UART0, 0xf, 0xf, -1, 0, 0, -1}, 33 {PERIPH_ID_UART1, 0xf, 0xf, -1, 4, 4, -1}, 34 {PERIPH_ID_UART2, 0xf, 0xf, -1, 8, 8, -1}, 35 {PERIPH_ID_UART3, 0xf, 0xf, -1, 12, 12, -1}, 36 {PERIPH_ID_I2C0, -1, 0x7, 0x7, -1, 24, 0}, 37 {PERIPH_ID_I2C1, -1, 0x7, 0x7, -1, 24, 0}, 38 {PERIPH_ID_I2C2, -1, 0x7, 0x7, -1, 24, 0}, 39 {PERIPH_ID_I2C3, -1, 0x7, 0x7, -1, 24, 0}, [all …]
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/openbmc/linux/sound/soc/meson/ |
H A D | axg-frddr.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 11 #include <linux/clk.h> 17 #include <sound/soc-dai.h> 19 #include "axg-fifo.h" 41 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare() 43 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare() 45 regmap_update_bits(fifo->map, FIFO_CTRL1, in g12a_frddr_dai_prepare() 61 depth = min(period, fifo->depth); in axg_frddr_dai_hw_params() 62 val = (depth / AXG_FIFO_BURST) - 1; in axg_frddr_dai_hw_params() 63 regmap_update_bits(fifo->map, FIFO_CTRL1, CTRL1_FRDDR_DEPTH, in axg_frddr_dai_hw_params() [all …]
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H A D | t9015.c | 1 // SPDX-License-Identifier: GPL-2.0 6 #include <linux/clk.h> 56 struct snd_soc_component *component = dai->component; in t9015_dai_set_fmt() 69 return -EINVAL; in t9015_dai_set_fmt() 76 return -EINVAL; in t9015_dai_set_fmt() 86 .name = "t9015-hifi", 100 static const DECLARE_TLV_DB_MINMAX_MUTE(dac_vol_tlv, -9525, 0); 137 SND_SOC_DAPM_MUX("Right DAC Sel", SND_SOC_NOPM, 0, 0, 139 SND_SOC_DAPM_MUX("Left DAC Sel", SND_SOC_NOPM, 0, 0, 143 SND_SOC_DAPM_OUT_DRV("Right- Driver", BLOCK_EN, LORN_EN, 0, [all …]
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H A D | axg-spdifout.c | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT) 6 #include <linux/clk.h> 11 #include <sound/soc-dai.h> 19 * applied when the related sel bits are cleared 61 struct clk *mclk; 62 struct clk *pclk; 97 axg_spdifout_enable(priv->map); in axg_spdifout_trigger() 103 axg_spdifout_disable(priv->map); in axg_spdifout_trigger() 107 return -EINVAL; in axg_spdifout_trigger() 116 regmap_update_bits(priv->map, SPDIFOUT_CTRL0, SPDIFOUT_CTRL0_VSET, in axg_spdifout_mute() [all …]
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/openbmc/linux/Documentation/devicetree/bindings/media/ |
H A D | mediatek,vcodec-subdev-decoder.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 4 --- 5 $id: http://devicetree.org/schemas/media/mediatek,vcodec-subdev-decoder.yaml# 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Yunfei Dong <yunfei.dong@mediatek.com> 20 +------------------------------------------------+-------------------------------------+ 22 | input -> lat soc HW -> lat HW -> lat buffer --|--> lat buffer -> core HW -> output | 24 +------------||-------------||-------------------+---------------------||--------------+ 26 -------------||-------------||-------------------|---------------------||--------------- 27 ||<------------||----------------HW index---------------->|| <child> [all …]
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/openbmc/linux/drivers/mmc/host/ |
H A D | sdhci_am654.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com 8 #include <linux/clk.h> 18 #include "sdhci-cqhci.h" 19 #include "sdhci-pltfm.h" 88 #define SDHCI_AM654_AUTOSUSPEND_DELAY -1 107 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 108 "ti,itap-del-sel-legacy", 110 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", [all …]
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/openbmc/linux/drivers/clk/imx/ |
H A D | clk-imx6q.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 3 * Copyright 2011-2013 Freescale Semiconductor, Inc. 10 #include <linux/clk.h> 12 #include <linux/clk-provider.h> 15 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> 20 #include <dt-bindings/clock/imx6qdl-clock.h> 22 #include "clk.h" 154 return -ENOENT; in ldb_di_sel_by_clock_id() 165 return -ENOENT; in ldb_di_sel_by_clock_id() 175 int parent, child, sel; in of_assigned_ldb_sels() local [all …]
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/openbmc/linux/arch/arm/boot/dts/nxp/ls/ |
H A D | ls1021a-tqmls1021a-mbls1021a.dts | 1 // SPDX-License-Identifier: (GPL-2.0-or-later OR X11) 3 * Copyright 2013-2014 Freescale Semiconductor, Inc. 4 * Copyright 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, 5 * D-82229 Seefeld, Germany. 9 /dts-v1/; 11 #include <dt-bindings/gpio/gpio.h> 12 #include <dt-bindings/input/linux-event-codes.h> 13 #include <dt-bindings/leds/common.h> 14 #include <dt-bindings/leds/leds-pca9532.h> 15 #include <dt-bindings/net/ti-dp83867.h> [all …]
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/openbmc/linux/arch/arm64/boot/dts/mediatek/ |
H A D | mt2712e.dtsi | 5 * SPDX-License-Identifier: (GPL-2.0 OR MIT) 8 #include <dt-bindings/clock/mt2712-clk.h> 9 #include <dt-bindings/interrupt-controller/irq.h> 10 #include <dt-bindings/interrupt-controller/arm-gic.h> 11 #include <dt-bindings/memory/mt2712-larb-port.h> 12 #include <dt-bindings/phy/phy.h> 13 #include <dt-bindings/power/mt2712-power.h> 14 #include "mt2712-pinfunc.h" 18 interrupt-parent = <&sysirq>; 19 #address-cells = <2>; [all …]
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/openbmc/linux/drivers/regulator/ |
H A D | stm32-vrefbuf.c | 1 // SPDX-License-Identifier: GPL-2.0-only 9 #include <linux/clk.h> 32 struct clk *clk; member 47 ret = pm_runtime_resume_and_get(priv->dev); in stm32_vrefbuf_enable() 51 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_enable() 53 writel_relaxed(val, priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_enable() 57 * VRR to be set. That means output has reached expected value. in stm32_vrefbuf_enable() 61 ret = readl_poll_timeout(priv->base + STM32_VREFBUF_CSR, val, in stm32_vrefbuf_enable() 64 dev_err(&rdev->dev, "stm32 vrefbuf timed out!\n"); in stm32_vrefbuf_enable() 65 val = readl_relaxed(priv->base + STM32_VREFBUF_CSR); in stm32_vrefbuf_enable() [all …]
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