Lines Matching +full:clk +full:- +full:output +full:- +full:sel

31 #define NPCM7XX_WATCHDOG_RESET_GPIO_IN "npcm7xx-clk-watchdog-reset-gpio-in"
33 /* Maximum amount of clock inputs in a SEL module. */
36 /* PLLs in CLK module. */
45 /* SEL/MUX in CLK module. */
59 /* Dividers in CLK module. */
88  * struct NPCM7xxClockPLLState - A PLL module in CLK module.
90  * @clk: The CLK module that owns this module.
92  * @clock_out: The output clock of this module.
99     NPCMCLKState *clk;  member
107  * struct NPCM7xxClockSELState - A SEL module in CLK module.
109  * @clk: The CLK module that owns this module.
112  * @clock_out: The output clocks of this module.
120     NPCMCLKState *clk;  member
130  * struct NPCM7xxClockDividerState - A Divider module in CLK module.
132  * @clk: The CLK module that owns this module.
134  * @clock_out: The output clock of this module.
145     NPCMCLKState *clk;  member
190 #define TYPE_NPCM_CLK "npcm-clk"
192 #define TYPE_NPCM7XX_CLK "npcm7xx-clk"
193 #define TYPE_NPCM8XX_CLK "npcm8xx-clk"