/openbmc/linux/drivers/clk/nxp/ |
H A D | clk-lpc32xx.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 12 #include <dt-bindings/clock/lpc32xx-clock.h> 165 static struct clk *clk[LPC32XX_CLK_MAX]; variable 167 .clks = clk, 171 static struct clk *usb_clk[LPC32XX_USB_CLK_MAX]; 253 * divider register does not contain information about selected rate. 329 enum clk_pll_mode mode; member 378 static inline u32 lpc32xx_usb_clk_read(struct lpc32xx_usb_clk *clk) in lpc32xx_usb_clk_read() argument [all …]
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/openbmc/linux/drivers/clk/davinci/ |
H A D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0 7 * Based on arch/arm/mach-davinci/clock.c 8 * Copyright (C) 2006-2007 Texas Instruments. 9 * Copyright (C) 2008-2009 Deep Root Systems, LLC 12 #include <linux/clk-provider.h> 13 #include <linux/clk.h> 14 #include <linux/clk/davinci.h> 24 #include <linux/platform_data/clk-davinci-pll.h> 80 * OMAP-L138 system reference guide recommends a wait for 4 OSCIN/CLKIN 81 * cycles to ensure that the PLLC has switched to bypass mode. Delay of 1us [all …]
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/openbmc/linux/drivers/clk/ |
H A D | clk-cdce925.c | 5 * Y4/Y5 to PLL2, and so on. PLL frequency is set on a first-come-first-serve 7 * deliver using the standard clk framework. In addition, the device can 13 #include <linux/clk.h> 14 #include <linux/clk-provider.h> 68 u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */ 87 struct clk_cdce925_output clk[MAX_NUMBER_OF_OUTPUTS]; member 96 return parent_rate; /* In bypass mode runs at same frequency */ in cdce925_pll_calculate_rate() 106 return cdce925_pll_calculate_rate(parent_rate, data->n, data->m); in cdce925_pll_recalc_rate() 117 /* Can always deliver parent_rate in bypass mode */ in cdce925_pll_find_rate() 122 /* In PLL mode, need to apply min/max range */ in cdce925_pll_find_rate() [all …]
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/openbmc/linux/drivers/clk/zynqmp/ |
H A D | pll.c | 1 // SPDX-License-Identifier: GPL-2.0 5 * Copyright (C) 2016-2018 Xilinx 8 #include <linux/clk.h> 9 #include <linux/clk-provider.h> 11 #include "clk-zynqmp.h" 14 * struct zynqmp_pll - PLL clock 15 * @hw: Handle between common and hardware-specific interfaces 44 * zynqmp_pll_get_mode() - Get mode of PLL 45 * @hw: Handle between common and hardware-specific interfaces 47 * Return: Mode of PLL [all …]
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/openbmc/linux/drivers/spi/ |
H A D | spi-orion.c | 1 // SPDX-License-Identifier: GPL-2.0-only 6 * Copyright (C) 2007-2008 Marvell Ltd. 19 #include <linux/clk.h> 45 /* Register for the "Direct Mode" */ 73 * have both is for managing the armada-370-spi case with old 95 struct clk *clk; member 96 struct clk *axi_clk; 110 return orion_spi->base + reg; in spi_reg() 144 orion_spi = spi_controller_get_devdata(spi->controller); in orion_spi_baudrate_set() 145 devdata = orion_spi->devdata; in orion_spi_baudrate_set() [all …]
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H A D | spi-meson-spicc.c | 7 * SPDX-License-Identifier: GPL-2.0+ 11 #include <linux/clk.h> 12 #include <linux/clk-provider.h> 29 * The PIO mode is the only mode implemented, and due to badly designed HW : 30 * - all transfers are cutted in 16 words burst because the FIFO hangs on 31 * TX underflow, and there is no TX "Half-Empty" interrupt, so we go by 33 * - CS management is dumb, and goes UP between every burst, so is really a 69 #define SPICC_TH_EN BIT(1) /* TX FIFO Half-Full Interrupt */ 72 #define SPICC_RH_EN BIT(4) /* RX FIFO Half-Full Interrupt */ 89 #define SPICC_TH BIT(1) /* TX FIFO Half-Full Interrupt */ [all …]
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/openbmc/linux/drivers/gpu/ipu-v3/ |
H A D | ipu-di.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later 4 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc. 14 #include <video/imx-ipu-v3.h> 15 #include "ipu-prv.h" 21 struct clk *clk_di; /* display input clock */ 22 struct clk *clk_ipu; /* IPU bus clock */ 23 struct clk *clk_di_pixel; /* resulting pixel clock */ 76 #define DI_SW_GEN0(gen) (0x000c + 4 * ((gen) - 1)) 77 #define DI_SW_GEN1(gen) (0x0030 + 4 * ((gen) - 1)) 78 #define DI_STP_REP(gen) (0x0148 + 4 * (((gen) - 1)/2)) [all …]
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/openbmc/u-boot/arch/arm/mach-snapdragon/ |
H A D | clock-snapdragon.c | 1 // SPDX-License-Identifier: BSD-3-Clause 11 #include <clk-uclass.h> 16 #include "clock-snapdragon.h" 22 extern ulong msm_set_rate(struct clk *clk, ulong rate); 35 if (readl(base + gpll0->status) & gpll0->status_bit) in clk_enable_gpll0() 38 setbits_le32(base + gpll0->ena_vote, gpll0->vote_bit); in clk_enable_gpll0() 40 while ((readl(base + gpll0->status) & gpll0->status_bit) == 0) in clk_enable_gpll0() 52 setbits_le32(base + vclk->ena_vote, vclk->vote_bit); in clk_enable_vote_clk() 54 val = readl(base + vclk->cbcr_reg); in clk_enable_vote_clk() 71 #define CFG_MODE_DUAL_EDGE (0x2 << 12) /* Counter mode */ [all …]
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/openbmc/linux/Documentation/devicetree/bindings/iio/frequency/ |
H A D | adi,adf4350.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Michael Hennerich <michael.hennerich@analog.com> 15 - adi,adf4350 16 - adi,adf4351 21 spi-max-frequency: 28 clock-names: 35 adi,channel-spacing: 40 adi,power-up-frequency: [all …]
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/openbmc/linux/drivers/clk/ti/ |
H A D | dpll3xxx.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * OMAP3/4 - specific DPLL control functions 5 * Copyright (C) 2009-2010 Texas Instruments, Inc. 6 * Copyright (C) 2009-2010 Nokia Corporation 23 #include <linux/clk.h> 27 #include <linux/clk/ti.h> 40 static u32 omap3_dpll_autoidle_read(struct clk_hw_omap *clk); 41 static void omap3_dpll_deny_idle(struct clk_hw_omap *clk); 42 static void omap3_dpll_allow_idle(struct clk_hw_omap *clk); 46 /* _omap3_dpll_write_clken - write clken_bits arg to a DPLL's enable bits */ [all …]
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H A D | clkt_dpll.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2005-2008 Texas Instruments, Inc. 6 * Copyright (C) 2004-2010 Nokia Corporation 9 * Richard Woodruff <r-woodruff2@ti.com> 16 #include <linux/clk.h> 17 #include <linux/clk-provider.h> 19 #include <linux/clk/ti.h> 25 /* DPLL rate rounding: minimum DPLL multiplier, divider values */ 30 #define DPLL_MULT_UNDERFLOW -1 51 #define DPLL_FINT_UNDERFLOW -1 [all …]
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H A D | fapll.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 #include <linux/clk.h> 4 #include <linux/clk-provider.h> 11 #include <linux/clk/ti.h> 49 /* Synthesizer divider register */ 63 struct clk *clk_ref; 64 struct clk *clk_bypass; 76 struct clk *clk_pll; 81 u32 v = readl_relaxed(fd->base); in ti_fapll_clock_is_bypass() 83 if (fd->bypass_bit_inverted) in ti_fapll_clock_is_bypass() [all …]
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/openbmc/linux/drivers/clk/renesas/ |
H A D | rcar-gen3-cpg.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 3 * R-Car Gen3 Clock Pulse Generator 5 * Copyright (C) 2015-2018 Glider bvba 23 CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */ 26 CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */ 27 CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */ 29 CLK_TYPE_GEN3_E3_RPCSRC,/* Select parent/divider using RPCCKCR.DIV */ 82 struct clk *rcar_gen3_cpg_clk_register(struct device *dev, 84 struct clk **clks, void __iomem *base, 87 unsigned int clk_extalr, u32 mode);
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H A D | rcar-gen4-cpg.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 3 * R-Car Gen4 Clock Pulse Generator 25 CLK_TYPE_GEN4_MDSEL, /* Select parent/divider using mode pin */ 27 CLK_TYPE_GEN4_OSC, /* OSC EXTAL predivider and fixed divider */ 73 struct clk *rcar_gen4_cpg_clk_register(struct device *dev, 75 struct clk **clks, void __iomem *base, 78 unsigned int clk_extalr, u32 mode);
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/openbmc/linux/drivers/gpu/drm/nouveau/nvkm/subdev/clk/ |
H A D | gk20a.c | 2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved. 48 for (pl = 0; pl < ARRAY_SIZE(_pl_to_div) - 1; pl++) { in div_to_pl() 53 return ARRAY_SIZE(_pl_to_div) - 1; in div_to_pl() 65 gk20a_pllg_read_mnp(struct gk20a_clk *clk, struct gk20a_pll *pll) in gk20a_pllg_read_mnp() argument 67 struct nvkm_device *device = clk->base.subdev.device; in gk20a_pllg_read_mnp() 71 pll->m = (val >> GPCPLL_COEFF_M_SHIFT) & MASK(GPCPLL_COEFF_M_WIDTH); in gk20a_pllg_read_mnp() 72 pll->n = (val >> GPCPLL_COEFF_N_SHIFT) & MASK(GPCPLL_COEFF_N_WIDTH); in gk20a_pllg_read_mnp() 73 pll->pl = (val >> GPCPLL_COEFF_P_SHIFT) & MASK(GPCPLL_COEFF_P_WIDTH); in gk20a_pllg_read_mnp() 77 gk20a_pllg_write_mnp(struct gk20a_clk *clk, const struct gk20a_pll *pll) in gk20a_pllg_write_mnp() argument 79 struct nvkm_device *device = clk->base.subdev.device; in gk20a_pllg_write_mnp() [all …]
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/openbmc/linux/drivers/i2c/busses/ |
H A D | i2c-mxs.c | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de> 6 * Copyright (C) 2011-2012 Wolfram Sang, Pengutronix e.K. 8 * based on a (non-working) driver which was: 10 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. 25 #include <linux/dma-mapping.h> 27 #include <linux/dma/mxs-dma.h> 29 #define DRIVER_NAME "mxs-i2c" 69 #define MXS_I2C_DATA(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x60 : 0xa0) 71 #define MXS_I2C_DEBUG0_CLR(i2c) ((i2c->dev_type == MXS_I2C_V1) ? 0x78 : 0xb8) [all …]
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/openbmc/u-boot/drivers/clk/ |
H A D | mpc83xx_clk.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 8 * enum ratio - Description of a core clock ratio 34 * struct corecnf - Description for a core clock configuration 36 * @vco_divider: VCO divider (Core VCO frequency = Core frequency * VCO divider) 44 * Table with all valid Core CSB frequency ratio / VCO divider combinations as 79 * enum reg_type - Register to read a field from 89 * enum mode_type - Description of how to read a specific frequency value 92 * as a divider for the CSB clock to compute the 99 * @TYPE_SPECIAL: The frequency is calculated in a non-standard way 109 /* Map of each clock index to its human-readable name */ [all …]
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/openbmc/u-boot/arch/arm/mach-socfpga/ |
H A D | clock_manager_arria10.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) 2016-2017 Intel Corporation 10 #include <clk.h> 11 #include <dm/device-internal.h> 80 { "vco0-psrc", offsetof(struct mainpll_cfg, vco0_psrc) }, 81 { "vco1-denom", offsetof(struct mainpll_cfg, vco1_denom) }, 82 { "vco1-numer", offsetof(struct mainpll_cfg, vco1_numer) }, 83 { "mpuclk-cnt", offsetof(struct mainpll_cfg, mpuclk_cnt) }, 84 { "mpuclk-src", offsetof(struct mainpll_cfg, mpuclk_src) }, 85 { "nocclk-cnt", offsetof(struct mainpll_cfg, nocclk_cnt) }, [all …]
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/openbmc/linux/drivers/clk/meson/ |
H A D | clk-dualdiv.c | 1 // SPDX-License-Identifier: GPL-2.0 9 * The AO Domain embeds a dual/divider to generate a more precise 10 * 32,768KHz clock for low-power suspend mode and CEC. 13 * | Div1 |-| Cnt1 | 15 * -| ______ ______ X--> Out 17 * | Div2 |-| Cnt2 | 21 * for each divider to set when the switching is done. 24 #include <linux/clk-provider.h> 27 #include "clk-regmap.h" 28 #include "clk-dualdiv.h" [all …]
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/openbmc/linux/include/linux/iio/frequency/ |
H A D | ad9523.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 38 * struct ad9523_channel_spec - Output channel configuration 42 * @sync_ignore_en: Ignore chip-level SYNC signal. 44 * @use_alt_clock_src: Channel divider uses alternative clk source. 46 * @driver_mode: Output driver mode (logic level family). 47 * @divider_phase: Divider initial phase after a SYNC. Range 0..63 48 LSB = 1/2 of a period of the divider input clock. 49 * @channel_divider: 10-bit channel divider. 106 * struct ad9523_platform_data - platform specific information 109 * @refa_diff_rcv_en: REFA differential/single-ended input selection. [all …]
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/openbmc/linux/include/linux/clk/ |
H A D | ti.h | 1 /* SPDX-License-Identifier: GPL-2.0-only */ 10 #include <linux/clk-provider.h> 14 * struct clk_omap_reg - OMAP register declaration 26 * struct dpll_data - DPLL registers and integration data 32 * @control_reg: register containing the DPLL mode bitfield 33 * @enable_mask: mask of the DPLL mode bitfield in @control_reg 40 * @max_multiplier: maximum valid non-bypass multiplier value (actual) 42 * @min_divider: minimum valid non-bypass divider value (actual) 43 * @max_divider: maximum valid non-bypass divider value (actual) 46 * @autoidle_reg: register containing the DPLL autoidle mode bitfield [all …]
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/openbmc/linux/drivers/phy/amlogic/ |
H A D | phy-meson-axg-mipi-dphy.c | 1 // SPDX-License-Identifier: GPL-2.0 13 #include <linux/clk.h> 33 * [11] mipi divider clk selection. 34 * 1: select the mipi DDRCLKHS from clock divider. 36 * [10] mipi clock divider control. 38 * [9] mipi divider output enable. 39 * [8] mipi divider counter enable. 44 * [3] force data byte lane in stop mode. 45 * [2] force data byte lane 0 in receiver mode. 52 /* [31] clk lane tx_hs_en control selection. [all …]
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/openbmc/linux/drivers/gpu/drm/renesas/rcar-du/ |
H A D | rcar_lvds.c | 1 // SPDX-License-Identifier: GPL-2.0 3 * R-Car LVDS Encoder 5 * Copyright (C) 2013-2018 Renesas Electronics Corporation 10 #include <linux/clk.h> 13 #include <linux/media-bus-format.h> 54 #define RCAR_LVDS_QUIRK_DUAL_LINK BIT(4) /* Supports dual-link operation */ 74 struct clk *mod; /* CPG module clock */ 75 struct clk *extal; /* External clock */ 76 struct clk *dotclkin[2]; /* External DU clocks */ 88 return ioread32(lvds->mmio + reg); in rcar_lvds_read() [all …]
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/openbmc/linux/sound/soc/stm/ |
H A D | stm32_i2s.c | 1 // SPDX-License-Identifier: GPL-2.0-only 5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 10 #include <linux/clk.h> 11 #include <linux/clk-provider.h> 136 #define I2S_CGFR_I2SDIV_MAX ((1 << (I2S_CGFR_I2SDIV_BIT_H -\ 137 I2S_CGFR_I2SDIV_SHIFT)) - 1) 198 #define STM32_I2S_IS_MASTER(x) ((x)->ms_flg == I2S_MS_MASTER) 199 #define STM32_I2S_IS_SLAVE(x) ((x)->ms_flg == I2S_MS_SLAVE) 205 * struct stm32_i2s_data - private data of I2S 220 * @lock_fd: lock to manage race conditions in full duplex mode [all …]
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/openbmc/linux/drivers/mfd/ |
H A D | fsl-imx25-tsadc.c | 1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2014-2015 Pengutronix, Markus Pargmann <mpa@pengutronix.de> 6 #include <linux/clk.h> 12 #include <linux/mfd/imx25-tsadc.h> 35 regmap_read(tsadc->regs, MX25_TSC_TGSR, &status); in mx25_tsadc_irq_handler() 38 generic_handle_domain_irq(tsadc->domain, 1); in mx25_tsadc_irq_handler() 41 generic_handle_domain_irq(tsadc->domain, 0); in mx25_tsadc_irq_handler() 49 struct mx25_tsadc *tsadc = d->host_data; in mx25_tsadc_domain_map() 67 struct device *dev = &pdev->dev; in mx25_tsadc_setup_irq() 68 struct device_node *np = dev->of_node; in mx25_tsadc_setup_irq() [all …]
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