/openbmc/u-boot/include/ |
H A D | spd.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 24 unsigned char clk_cycle; /* 9 SDRAM Cycle time at CL=X */ 25 unsigned char clk_access; /* 10 SDRAM Access from Clock at CL=X */ 38 unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time at CL=X-1 */ 39 unsigned char clk_access2; /* 24 SDRAM Access from Clock at CL=X-1 */ 40 unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time at CL=X-2 */ 41 unsigned char clk_access3; /* 26 Max Access from Clock at CL=X-2 */ 42 unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ member 44 unsigned char trcd; /* 29 Min RAS to CAS Delay (tRCD) */ member 62 unsigned char res[15]; /* 47-xx IDD in SPD and Reserved space */ [all …]
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H A D | ddr_spd.h | 1 /* SPDX-License-Identifier: GPL-2.0 */ 3 * Copyright 2008-2014 Freescale Semiconductor, Inc. 10 * Format from "JEDEC Standard No. 21-C, 23 unsigned char clk_cycle; /* 9 SDRAM Cycle time @ CL=X */ 24 unsigned char clk_access; /* 10 SDRAM Access from Clk @ CL=X (tAC) */ 37 unsigned char clk_cycle2; /* 23 Min SDRAM Cycle time @ CL=X-0.5 */ 39 Clk @ CL=X-0.5 (tAC) */ 40 unsigned char clk_cycle3; /* 25 Min SDRAM Cycle time @ CL=X-1 */ 41 unsigned char clk_access3; /* 26 Max Access from Clk @ CL=X-1 (tAC) */ 42 unsigned char trp; /* 27 Min Row Precharge Time (tRP)*/ member [all …]
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/openbmc/u-boot/arch/arm/mach-sunxi/dram_timings/ |
H A D | ddr3_1333.c | 13 u8 trcd = ns_to_t(15); in mctl_set_timing_params() local 19 u8 trp = ns_to_t(15); in mctl_set_timing_params() local 33 u8 tcl = 6; /* CL 12 */ in mctl_set_timing_params() 45 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ in mctl_set_timing_params() 48 writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */ in mctl_set_timing_params() 49 writel(0x40, &mctl_ctl->mr[1]); in mctl_set_timing_params() 50 writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */ in mctl_set_timing_params() 51 writel(0x0, &mctl_ctl->mr[3]); in mctl_set_timing_params() 54 writel(0x3, &mctl_ctl->lp3mr11); /* odt_en[7:4] */ in mctl_set_timing_params() 59 &mctl_ctl->dramtmg[0]); in mctl_set_timing_params() [all …]
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H A D | ddr2_v3s.c | 13 u8 trcd = ns_to_t(20); in mctl_set_timing_params() local 19 u8 trp = ns_to_t(15); in mctl_set_timing_params() local 33 u8 tcl = 3; /* CL 6 */ in mctl_set_timing_params() 45 u8 trd2wr = tcl + 2 + 1 - tcwl; /* RL + BL / 2 + 2 - WL */ in mctl_set_timing_params() 48 writel(0x263, &mctl_ctl->mr[0]); in mctl_set_timing_params() 49 writel(0x4, &mctl_ctl->mr[1]); in mctl_set_timing_params() 50 writel(0x0, &mctl_ctl->mr[2]); in mctl_set_timing_params() 51 writel(0x0, &mctl_ctl->mr[3]); in mctl_set_timing_params() 56 &mctl_ctl->dramtmg[0]); in mctl_set_timing_params() 58 &mctl_ctl->dramtmg[1]); in mctl_set_timing_params() [all …]
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H A D | lpddr3_stock.c | 13 u8 trcd = max(ns_to_t(24), 2); in mctl_set_timing_params() local 19 u8 trp = max(ns_to_t(27), 2); in mctl_set_timing_params() local 33 u8 tcl = 6; /* CL 12 */ in mctl_set_timing_params() 45 u8 trd2wr = tcl + 4 + 5 - tcwl + 1; in mctl_set_timing_params() 48 writel(0xc3, &mctl_ctl->mr[1]); /* nWR=8, BL8 */ in mctl_set_timing_params() 49 writel(0xa, &mctl_ctl->mr[2]); /* RL=12, WL=6 */ in mctl_set_timing_params() 50 writel(0x2, &mctl_ctl->mr[3]); /* 40 0hms PD/PU */ in mctl_set_timing_params() 55 &mctl_ctl->dramtmg[0]); in mctl_set_timing_params() 57 &mctl_ctl->dramtmg[1]); in mctl_set_timing_params() 60 &mctl_ctl->dramtmg[2]); in mctl_set_timing_params() [all …]
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/openbmc/u-boot/arch/arm/mach-sunxi/ |
H A D | dram_sun9i.c | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * (C) Copyright 2007-2015 10 * Philipp Tomsich <philipp.tomsich@theobroma-systems.com> 26 * Allwinner as part of the open-source bootloader release (refer to 27 * https://github.com/allwinner-zh/bootloader.git) and augments the upstream 36 * Note that the Zynq-documentation provides a very close match for the DDR 42 * (i.e. the rules for MEMC_FREQ_RATIO=2 from the Zynq-documentation apply). 48 * 1) Only DDR3 support is implemented, as our test platform (the A80-Q7 50 * 2) Only 2T-mode has been implemented and tested. 62 * The driver should be driven from a device-tree based configuration that [all …]
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/openbmc/u-boot/drivers/ddr/fsl/ |
H A D | ddr2_dimm_params.c | 1 // SPDX-License-Identifier: GPL-2.0 18 * --- ----- ------ 46 * Convert a two-nibble BCD value into a cycle time. 47 * While the spec calls for nano-seconds, picos are returned. 148 * shortest SPD-defined CAS latency. 156 * CL to be programmed for a value that is lower than those 160 * CAS latency de-rating based upon values JEDEC Standard No. 79-2C 161 * Table 40, "DDR2 SDRAM stanadard speed bins and tCK, tRCD, tRP, tRAS, 164 * ordinal 2, ddr2_speed_bins[1] contains tCK for CL=3 165 * Not certain if any good value exists for CL=2 [all …]
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/openbmc/u-boot/board/Seagate/nas220/ |
H A D | kwbimage.cfg | 2 # Copyright (C) 2014 Evgeni Dobrev <evgeni@studio-punkt.com> 9 # SPDX-License-Identifier: GPL-2.0+ 11 # Refer doc/README.kwbimage for more details about how-to configure 23 # Configure RGMII-0 interface pad voltage to 1.8V 26 #Dram initalization for SINGLE x16 CL=5 @ 400MHz 28 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate) 29 # bit23-14: zero 32 # bit29-26: zero 33 # bit31-30: 01 41 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 [all …]
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/openbmc/u-boot/board/mpr2/ |
H A D | lowlevel_init.S | 1 /* SPDX-License-Identifier: GPL-2.0+ */ 84 * Samsung K4S511632B-UL75 @ 48 MHz 85 * Micron MT48LC32M16A2-75 @ 48 MHz 89 /* tRP=1ck, tRCD=1ck, CL=2, tRWL=2ck, tRC=4ck */
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/openbmc/u-boot/board/LaCie/netspace_v2/ |
H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+ 8 # Written-by: Prafulla Wadaskar <prafulla@marvell.com> 9 # Refer doc/README.kwbimage for more details about how-to configure 19 # Configure RGMII-0 interface pad voltage to 1.8V 22 #Dram initalization for SINGLE x16 CL=5 @ 400MHz 24 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate) 25 # bit23-14: zero 28 # bit29-26: zero 29 # bit31-30: 01 37 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 [all …]
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H A D | kwbimage-is2.cfg | 1 # SPDX-License-Identifier: GPL-2.0+ 8 # Written-by: Prafulla Wadaskar <prafulla@marvell.com> 9 # Refer doc/README.kwbimage for more details about how-to configure 19 # Configure RGMII-0 interface pad voltage to 1.8V 22 #Dram initalization for SINGLE x16 CL=5 @ 400MHz 24 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate) 25 # bit23-14: zero 28 # bit29-26: zero 29 # bit31-30: 01 37 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 [all …]
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H A D | kwbimage-ns2l.cfg | 1 # SPDX-License-Identifier: GPL-2.0+ 8 # Written-by: Prafulla Wadaskar <prafulla@marvell.com> 9 # Refer doc/README.kwbimage for more details about how-to configure 19 # Configure RGMII-0 interface pad voltage to 1.8V 22 #Dram initalization for SINGLE x16 CL=5 @ 400MHz 24 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate) 25 # bit23-14: zero 28 # bit29-26: zero 29 # bit31-30: 01 37 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 [all …]
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/openbmc/u-boot/board/cloudengines/pogo_e02/ |
H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+ 9 # Written-by: Prafulla Wadaskar <prafulla <at> marvell.com> 10 # Refer doc/README.kwbimage for more details about how-to configure 22 # Configure RGMII-0 interface pad voltage to 1.8V 25 #Dram initalization for SINGLE x16 CL=5 @ 400MHz 27 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate) 28 # bit23-14: zero 31 # bit29-26: zero 32 # bit31-30: 01 40 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 [all …]
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/openbmc/u-boot/board/iomega/iconnect/ |
H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+ 3 # (C) Copyright 2009-2012 6 # Refer doc/README.kwbimage for more details about how-to configure 18 # Configure RGMII-0 interface pad voltage to 1.8V 21 # Dram initalization for SINGLE x16 CL=5 @ 400MHz 23 # bit13-0: 0xc30, (3120 DDR2 clks refresh rate) 24 # bit23-14: 0x0, 27 # bit29-26: 0x0, 28 # bit31-30: 0x1, 36 # bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 [all …]
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/openbmc/u-boot/board/LaCie/net2big_v2/ |
H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+ 8 # Written-by: Prafulla Wadaskar <prafulla@marvell.com> 9 # Refer doc/README.kwbimage for more details about how-to configure 19 # Configure RGMII-0 interface pad voltage to 1.8V 22 #Dram initalization for SINGLE x16 CL=5 @ 400MHz 24 # bit13-0: 0xa00 (2560 DDR2 clks refresh rate) 25 # bit23-14: zero 28 # bit29-26: zero 29 # bit31-30: 01 37 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 [all …]
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/openbmc/u-boot/board/Synology/ds109/ |
H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+ 4 # Jason Cooper <u-boot@lakedaemon.net> 8 # Written-by: Siddarth Gore <gores@marvell.com> 9 # Refer doc/README.kwbimage for more details about how-to configure 19 # Configure RGMII-0/1 interface pad voltage to 1.8V 25 #Dram initalization for SINGLE x16 CL=5 @ 400MHz 27 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate) 28 # bit23-14: zero 31 # bit29-26: zero 32 # bit31-30: 01 [all …]
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/openbmc/u-boot/board/Marvell/dreamplug/ |
H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+ 4 # Jason Cooper <u-boot@lakedaemon.net> 8 # Written-by: Siddarth Gore <gores@marvell.com> 9 # Refer doc/README.kwbimage for more details about how-to configure 19 # Configure RGMII-0/1 interface pad voltage to 1.8V 22 #Dram initalization for SINGLE x16 CL=5 @ 400MHz 24 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate) 25 # bit23-14: zero 28 # bit29-26: zero 29 # bit31-30: 01 [all …]
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/openbmc/u-boot/board/Marvell/sheevaplug/ |
H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+ 5 # Written-by: Prafulla Wadaskar <prafulla@marvell.com> 6 # Refer to doc/README.kwbimage for more details about how-to 18 # Configure RGMII-0 interface pad voltage to 1.8V 21 #Dram initalization for SINGLE x16 CL=5 @ 400MHz 23 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate) 24 # bit23-14: zero 27 # bit29-26: zero 28 # bit31-30: 01 36 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 [all …]
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/openbmc/u-boot/board/Marvell/guruplug/ |
H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+ 5 # Written-by: Siddarth Gore <gores@marvell.com> 6 # Refer doc/README.kwbimage for more details about how-to configure 18 # Configure RGMII-0/1 interface pad voltage to 1.8V 21 #Dram initalization for SINGLE x16 CL=5 @ 400MHz 23 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate) 24 # bit23-14: zero 27 # bit29-26: zero 28 # bit31-30: 01 36 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 [all …]
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/openbmc/u-boot/board/Seagate/dockstar/ |
H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+ 9 # Refer doc/README.kwbimage for more details about how-to configure 21 # Configure RGMII-0 interface pad voltage to 1.8V 24 #Dram initalization for SINGLE x16 CL=5 @ 400MHz 26 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate) 27 # bit23-14: zero 30 # bit29-26: zero 31 # bit31-30: 01 39 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 40 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM [all …]
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/openbmc/u-boot/board/Seagate/goflexhome/ |
H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+ 12 # Refer docs/README.kwimage for more details about how-to configure 24 # Configure RGMII-0 interface pad voltage to 1.8V 27 #Dram initalization for SINGLE x16 CL=5 @ 400MHz 29 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate) 30 # bit23-14: zero 33 # bit29-26: zero 34 # bit31-30: 01 42 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 43 # bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM [all …]
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/openbmc/u-boot/board/Marvell/openrd/ |
H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+ 5 # Written-by: Prafulla Wadaskar <prafulla@marvell.com> 6 # Refer doc/README.kwbimage for more details about how-to configure 18 # Configure RGMII-0 interface pad voltage to 1.8V 21 #Dram initalization for SINGLE x16 CL=5 @ 400MHz 23 # bit13-0: 0xc30 (3120 DDR2 clks refresh rate) 24 # bit23-14: zero 27 # bit29-26: zero 28 # bit31-30: 01 36 # bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 [all …]
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/openbmc/u-boot/board/raidsonic/ib62x0/ |
H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+ 3 # Copyright (C) 2011-2012 7 # Refer doc/README.kwbimage for more details about how-to configure 19 # Configure RGMII-0 interface pad voltage to 1.8V 22 # Dram initalization for SINGLE x16 CL=5 @ 400MHz 24 # bit13-0: 0xc30, (3120 DDR2 clks refresh rate) 25 # bit23-14: 0x0, 28 # bit29-26: 0x0, 29 # bit31-30: 0x1, 37 # bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0 [all …]
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/openbmc/u-boot/arch/powerpc/cpu/mpc83xx/ |
H A D | spd_sdram.c | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * (C) Copyright 2006-2007 Freescale Semiconductor, Inc. 8 * Copyright (C) 2004-2006 Freescale Semiconductor, Inc. 28 volatile ddr83xx_t *ddr = &immap->ddr; in board_add_ram_info() 31 printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) in board_add_ram_info() 32 >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1); in board_add_ram_info() 35 if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_16) in board_add_ram_info() 36 puts(", 16-bit"); in board_add_ram_info() 37 else if ((ddr->sdram_cfg & SDRAM_CFG_DBW_MASK) == SDRAM_CFG_DBW_32) in board_add_ram_info() 38 puts(", 32-bit"); in board_add_ram_info() [all …]
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/openbmc/u-boot/board/keymile/km_arm/ |
H A D | kwbimage.cfg | 1 # SPDX-License-Identifier: GPL-2.0+ 5 # Refer doc/README.kwbimage for more details about how-to configure 13 # bit 3-0: MPPSel0 2, NF_IO[2] 14 # bit 7-4: MPPSel1 2, NF_IO[3] 15 # bit 12-8: MPPSel2 2, NF_IO[4] 16 # bit 15-12: MPPSel3 2, NF_IO[5] 17 # bit 19-16: MPPSel4 1, NF_IO[6] 18 # bit 23-20: MPPSel5 1, NF_IO[7] 19 # bit 27-24: MPPSel6 1, SYSRST_O 20 # bit 31-28: MPPSel7 0, GPO[7] [all …]
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