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/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Ddra7xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 atl_clkin0_ck: clock-atl-clkin0 {
9 #clock-cells = <0>;
10 compatible = "ti,dra7-atl-clock";
11 clock-output-names = "atl_clkin0_ck";
15 atl_clkin1_ck: clock-atl-clkin1 {
16 #clock-cells = <0>;
17 compatible = "ti,dra7-atl-clock";
18 clock-output-names = "atl_clkin1_ck";
22 atl_clkin2_ck: clock-atl-clkin2 {
[all …]
H A Dam43xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 sys_clkin_ck: clock-sys-clkin-31@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <31>;
17 crystal_freq_sel_ck: clock-crystal-freq-sel-29@40 {
18 #clock-cells = <0>;
19 compatible = "ti,mux-clock";
20 clock-output-names = "crystal_freq_sel_ck";
[all …]
H A Dam33xx-clocks.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
8 sys_clkin_ck: clock-sys-clkin-22@40 {
9 #clock-cells = <0>;
10 compatible = "ti,mux-clock";
11 clock-output-names = "sys_clkin_ck";
13 ti,bit-shift = <22>;
17 adc_tsc_fck: clock-adc-tsc-fck {
18 #clock-cells = <0>;
19 compatible = "fixed-factor-clock";
20 clock-output-names = "adc_tsc_fck";
[all …]
/openbmc/u-boot/drivers/pinctrl/
H A Dpinctrl-at91.c1 // SPDX-License-Identifier: GPL-2.0+
29 #define PULL_UP BIT(0)
30 #define MULTI_DRIVE BIT(1)
31 #define DEGLITCH BIT(2)
32 #define PULL_DOWN BIT(3)
33 #define DIS_SCHMIT BIT(4)
37 #define OUTPUT BIT(7)
40 #define DEBOUNCE BIT(16)
67 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
68 * on new IP with support for periph C and D the way to mux in
[all …]
/openbmc/u-boot/drivers/ddr/marvell/axp/
H A Dddr3_pbs.c1 // SPDX-License-Identifier: GPL-2.0
44 /* PBS locked dq (per pup) */
92 /* bit array for unlock pups - used to repeat on the RX operation */ in ddr3_pbs_tx()
102 DEBUG_PBS_S("DDR3 - PBS TX - Starting PBS TX procedure\n"); in ddr3_pbs_tx()
104 pups = dram_info->num_of_total_pups; in ddr3_pbs_tx()
105 max_pup = dram_info->num_of_total_pups; in ddr3_pbs_tx()
110 /* [0] = 1 - Enable SW override */ in ddr3_pbs_tx()
111 /* 0x15B8 - Training SW 2 Register */ in ddr3_pbs_tx()
113 DEBUG_PBS_S("DDR3 - PBS RX - SW Override Enabled\n"); in ddr3_pbs_tx()
116 reg_write(REG_DRAM_TRAINING_ADDR, reg); /* 0x15B0 - Training Register */ in ddr3_pbs_tx()
[all …]
/openbmc/u-boot/arch/arm/mach-mvebu/serdes/axp/
H A Dhigh_speed_env_spec.h1 /* SPDX-License-Identifier: GPL-2.0 */
46 * Configuration per SERDES line. Each nibble is MV_SERDES_LINE_TYPE
50 u32 line0_7; /* Lines 0 to 7 SERDES MUX one nibble per line */
51 u32 line8_15; /* Lines 8 to 15 SERDES MUX one nibble per line */
55 * Bus speed - one bit per SERDES line:
57 * PEX 2.5 G (10 bit) 5 G (20 bit)
68 {0, 1, -1 , -1, -1, -1, -1, -1, -1}, /* Lane 0 */ \
69 {0, 1, -1 , -1, -1, -1, -1, -1, 2}, /* Lane 1 */ \
70 {0, 1, -1 , 2, -1, -1, -1, -1, 3}, /* Lane 2 */ \
71 {0, 1, -1 , -1, 2, -1, -1, 3, -1}, /* Lane 3 */ \
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/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dbrcm,bcm2835-gpio.txt7 - compatible: "brcm,bcm2835-gpio"
8 - compatible: should be one of:
9 "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl
10 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
11 "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl
12 "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl
13 - reg: Should contain the physical address of the GPIO module's registers.
14 - gpio-controller: Marks the device node as a GPIO controller.
15 - #gpio-cells : Should be two. The first cell is the pin number and the
17 - bit 0 specifies polarity (0 for normal, 1 for inverted)
[all …]
H A Dpinctrl-single.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/pinctrl-single.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Tony Lindgren <tony@atomide.com>
21 - enum:
22 - pinctrl-single
23 - pinconf-single
24 - items:
25 - enum:
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/openbmc/u-boot/drivers/pinctrl/rockchip/
H A Dpinctrl-rockchip-core.c1 // SPDX-License-Identifier: GPL-2.0+
13 #include "pinctrl-rockchip.h"
22 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_verify_config()
24 if (bank >= ctrl->nr_banks) { in rockchip_verify_config()
25 debug("pin conf bank %d >= nbanks %d\n", bank, ctrl->nr_banks); in rockchip_verify_config()
26 return -EINVAL; in rockchip_verify_config()
32 return -EINVAL; in rockchip_verify_config()
39 int *reg, u8 *bit, int *mask) in rockchip_get_recalced_mux() argument
41 struct rockchip_pinctrl_priv *priv = bank->priv; in rockchip_get_recalced_mux()
42 struct rockchip_pin_ctrl *ctrl = priv->ctrl; in rockchip_get_recalced_mux()
[all …]
/openbmc/linux/sound/pci/ca0106/
H A Dca0106.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (c) 2004 James Courtier-Dutton <James@superbug.demon.co.uk>
4 * Driver CA0106 chips. e.g. Sound Blaster Audigy LS and Live 24bit
11 * Support interrupts per period.
48 * Added GPIO info for SB Live 24bit.
50 * Implement support for Line-in capture on SB Live 24bit.
52 * Add support for mute control on SB Live 24bit (cards w/ SPI DAC)
73 #define IPR_MIDI_RX_B 0x00020000 /* MIDI UART-B Receive buffer non-empty */
74 #define IPR_MIDI_TX_B 0x00010000 /* MIDI UART-B Transmit buffer empty */
87 #define IPR_MIDI_RX_A 0x00000004 /* MIDI UART-A Receive buffer non-empty */
[all …]
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx7s.dtsi1 // SPDX-License-Identifier: GPL-2.0+ OR MIT
6 #include <dt-bindings/clock/imx7d-clock.h>
7 #include <dt-bindings/power/imx7-power.h>
8 #include <dt-bindings/gpio/gpio.h>
9 #include <dt-bindings/input/input.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/reset/imx7-reset.h>
12 #include "imx7d-pinfunc.h"
15 #address-cells = <1>;
16 #size-cells = <1>;
[all …]
H A Dimx6qdl.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/input/input.h>
8 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
15 * pre-existing /chosen node to be available to insert the
58 compatible = "fixed-clock";
59 #clock-cells = <0>;
60 clock-frequency = <32768>;
[all …]
/openbmc/linux/include/net/
H A Dkcm.h1 /* SPDX-License-Identifier: GPL-2.0-only */
60 struct kcm_mux *mux; member
76 /* Don't use bit fields here, these are set under different locks */
93 struct kcm_mux *mux; member
123 /* Per net MUX list */
133 /* Structure for a MUX */
139 struct list_head kcm_socks; /* All KCM sockets on MUX */
140 int kcm_socks_cnt; /* Total KCM socket count for MUX */
141 struct list_head psocks; /* List of all psocks on MUX */
155 spinlock_t lock ____cacheline_aligned_in_smp; /* TX and mux locking */
[all …]
/openbmc/linux/arch/hexagon/include/asm/
H A Dbitops.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Bit operations for the Hexagon architecture
5 * Copyright (c) 2010-2011, The Linux Foundation. All rights reserved.
20 * (i.e. I get to shift by #5-2 (32 bits per long, 4 bytes per access),
23 * Typically, R10 is clobbered for address, R11 bit nr, and R12 is temp
27 * test_and_clear_bit - clear a bit and return its old value
28 * @nr: bit number to clear
41 " {if (!P1) jump 1b; %0 = mux(P0,#1,#0);}\n" in test_and_clear_bit()
51 * test_and_set_bit - set a bit and return its old value
52 * @nr: bit number to set
[all …]
/openbmc/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dbrcm,bcm7120-l2-intc.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,bcm7120-l2-intc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom BCM7120-style Level 2 and Broadcom BCM3380 Level 1 / Level 2
10 - Florian Fainelli <f.fainelli@gmail.com>
14 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
19 - outputs multiple interrupts signals towards its interrupt controller parent
21 - controls how some of the interrupts will be flowing, whether they will
26 - has one 32-bit enable word and one 32-bit status word
[all …]
/openbmc/linux/include/linux/mfd/
H A Dintel-m10-bmc.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 * Copyright (C) 2018-2020 Intel Corporation, Inc.
55 #define DRBL_RSU_REQUEST BIT(0)
59 #define DRBL_PKVL_EEPROM_LOAD_SEC BIT(24)
60 #define DRBL_PKVL1_POLL_EN BIT(25)
61 #define DRBL_PKVL2_POLL_EN BIT(26)
62 #define DRBL_CONFIG_SEL BIT(28)
63 #define DRBL_REBOOT_REQ BIT(29)
64 #define DRBL_REBOOT_DISABLED BIT(30)
126 /* Address of 4KB inverted bit vector containing staging area FLASH count */
[all …]
/openbmc/linux/sound/soc/codecs/
H A Dlpass-tx-macro.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
12 #include <sound/soc-dapm.h>
15 #include <linux/clk-provider.h>
17 #include "lpass-macro-common.h"
20 #define CDC_TX_MCLK_EN_MASK BIT(0)
21 #define CDC_TX_MCLK_ENABLE BIT(0)
23 #define CDC_TX_FS_CNT_EN_MASK BIT(0)
24 #define CDC_TX_FS_CNT_ENABLE BIT(0)
26 #define CDC_TX_SWR_RESET_MASK BIT(1)
[all …]
/openbmc/linux/sound/soc/sunxi/
H A Dsun8i-codec.c1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * (C) Copyright 2010-2016
9 * Mylène Josserand <mylene.josserand@free-electrons.com>
23 #include <sound/soc-dapm.h>
200 regcache_cache_only(scodec->regmap, false); in sun8i_codec_runtime_resume()
202 ret = regcache_sync(scodec->regmap); in sun8i_codec_runtime_resume()
215 regcache_cache_only(scodec->regmap, true); in sun8i_codec_runtime_suspend()
216 regcache_mark_dirty(scodec->regmap); in sun8i_codec_runtime_suspend()
252 return -EINVAL; in sun8i_codec_get_hw_rate()
262 struct sun8i_codec_aif *aif = &scodec->aifs[i]; in sun8i_codec_update_sample_rate()
[all …]
/openbmc/linux/drivers/pinctrl/meson/
H A Dpinctrl-meson.h1 /* SPDX-License-Identifier: GPL-2.0-only */
20 * struct meson_pmx_group - a pinmux group
26 * @reg: register offset for the group in the domain mux registers
27 * @bit bit index enabling the group
38 * struct meson_pmx_func - a pinmux function
51 * struct meson_reg_desc - a register descriptor
54 * @bit: bit index in register
57 * pull-enable, direction, etc. for a single pin
61 unsigned int bit; member
65 * enum meson_reg_type - type of registers encoded in @meson_reg_desc
[all …]
/openbmc/linux/drivers/media/pci/dt3155/
H A Ddt3155.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * Copyright (C) 2006-2010 by Marin Mitov *
15 #include <media/v4l2-device.h>
16 #include <media/v4l2-dev.h>
17 #include <media/videobuf2-v4l2.h>
69 /* CSR1 bit masks */
88 /* INT_CSR bit masks */
96 /* IIC_CSR1 bit masks */
99 /* IIC_CSR2 bit masks */
105 /* CSR2 bit masks */
[all …]
/openbmc/linux/drivers/pinctrl/nomadik/
H A Dpinctrl-ab8505.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) ST-Ericsson SA 2012
5 * Author: Patrice Chotard <patrice.chotard@stericsson.com> for ST-Ericsson.
13 #include "pinctrl-abx500.h"
98 * The groups are arranged as sets per altfunction column, so we can
99 * mux in one group at a time by selecting the same altfunction for them
241 * ALTERNATE_FUNCTIONS(GPIO_NUMBER, GPIOSEL bit, ALTERNATFUNC bit1,
247 * means that pin AB8505_PIN_D18 (pin 13) supports 4 mux (default/ALT_A,
249 * select the mux. ALTA, ALTB and ALTC val indicates values to write in
251 * designers didn't apply the same logic on how to select mux in the
[all …]
/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * With some ideas taken from pinctrl-samsung:
14 * and pinctrl-at91:
15 * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
30 #include <linux/pinctrl/pinconf-generic.h>
37 #include <dt-bindings/pinctrl/rockchip.h>
41 #include "pinctrl-rockchip.h"
44 * Generate a bitmask for setting a value (v) with a write mask bit in hiword
53 #define IOMUX_GPIO_ONLY BIT(0)
54 #define IOMUX_WIDTH_4BIT BIT(1)
[all …]
/openbmc/linux/drivers/pinctrl/freescale/
H A Dpinctrl-imx1-core.c1 // SPDX-License-Identifier: GPL-2.0+
8 // Based on pinctrl-imx.c:
29 #include "pinctrl-imx1.h"
56 #define MX1_MUX_FUNCTION(val) (BIT(0) & val)
57 #define MX1_MUX_GPIO(val) ((BIT(1) & val) >> 1)
58 #define MX1_MUX_DIR(val) ((BIT(2) & val) >> 2)
59 #define MX1_MUX_OCONF(val) (((BIT(4) | BIT(5)) & val) >> 4)
60 #define MX1_MUX_ICONFA(val) (((BIT(8) | BIT(9)) & val) >> 8)
61 #define MX1_MUX_ICONFB(val) (((BIT(10) | BIT(11)) & val) >> 10)
69 * Those controls that are represented by 1 bit have a direct mapping between
[all …]
/openbmc/linux/drivers/media/pci/cx18/
H A Dcx23418.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
11 #include <media/drv-intf/cx2341x.h>
19 IN[0] - Task ID. This is one of the XPU_CMD_MASK_YYY where XPU is
21 OUT[0] - Task handle. This handle is passed along with commands to
23 ReturnCode - One of the ERR_SYS_... */
27 IN[0] - Task handle. Hanlde of the task to destroy
28 ReturnCode - One of the ERR_SYS_... */
49 IN[0] - audio parameters (same as CX18_CPU_SET_AUDIO_PARAMETERS?)
50 IN[1] - caller buffer address, or 0
51 ReturnCode - ??? */
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dimx6qdl.dtsi1 // SPDX-License-Identifier: GPL-2.0+
6 #include <dt-bindings/clock/imx6qdl-clock.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
10 #address-cells = <1>;
11 #size-cells = <1>;
14 * pre-existing /chosen node to be available to insert the
16 * Also for U-Boot there must be a pre-existing /memory node.
55 compatible = "fsl,imx-ckil", "fixed-clock";
56 #clock-cells = <0>;
57 clock-frequency = <32768>;
[all …]

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