Lines Matching +full:bit +full:- +full:per +full:- +full:mux
1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
5 #include <linux/clk-provider.h>
16 #include <sound/soc-dapm.h>
19 #include "lpass-macro-common.h"
23 #define CDC_VA_MCLK_CONTROL_EN BIT(0)
25 #define CDC_VA_FS_CONTROL_EN BIT(0)
26 #define CDC_VA_FS_COUNTER_CLR BIT(1)
28 #define CDC_VA_SWR_RESET_MASK BIT(1)
29 #define CDC_VA_SWR_RESET_ENABLE BIT(1)
30 #define CDC_VA_SWR_CLK_EN_MASK BIT(0)
31 #define CDC_VA_SWR_CLK_ENABLE BIT(0)
33 #define CDC_VA_FS_BROADCAST_EN BIT(1)
38 #define CDC_VA_DMIC_EN_MASK BIT(0)
39 #define CDC_VA_DMIC_ENABLE BIT(0)
49 #define CDC_VA_RESET_ALL_DMICS_MASK BIT(7)
50 #define CDC_VA_RESET_ALL_DMICS_RESET BIT(7)
52 #define CDC_VA_DMIC3_FREQ_CHANGE_MASK BIT(3)
53 #define CDC_VA_DMIC3_FREQ_CHANGE_EN BIT(3)
54 #define CDC_VA_DMIC2_FREQ_CHANGE_MASK BIT(2)
55 #define CDC_VA_DMIC2_FREQ_CHANGE_EN BIT(2)
56 #define CDC_VA_DMIC1_FREQ_CHANGE_MASK BIT(1)
57 #define CDC_VA_DMIC1_FREQ_CHANGE_EN BIT(1)
58 #define CDC_VA_DMIC0_FREQ_CHANGE_MASK BIT(0)
59 #define CDC_VA_DMIC0_FREQ_CHANGE_EN BIT(0)
85 #define CDC_VA_TX_PATH_CLK_EN_MASK BIT(5)
86 #define CDC_VA_TX_PATH_CLK_EN BIT(5)
88 #define CDC_VA_TX_PATH_PGA_MUTE_EN_MASK BIT(4)
89 #define CDC_VA_TX_PATH_PGA_MUTE_EN BIT(4)
103 #define CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_MASK BIT(1)
104 #define CDC_VA_TX_HPF_CUTOFF_FREQ_CHANGE_REQ BIT(1)
105 #define CDC_VA_TX_HPF_ZERO_GATE_MASK BIT(0)
106 #define CDC_VA_TX_HPF_ZERO_NO_GATE BIT(0)
137 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_MASK BIT(7)
138 #define CDC_VA_TX_PATH_ADC_DMIC_SEL_DMIC BIT(7)
165 static const DECLARE_TLV_DB_SCALE(digital_gain, -8400, 100, -8400);
443 struct regmap *regmap = va->regmap; in va_clk_rsc_fs_gen_request()
476 struct regmap *regmap = va->regmap; in va_macro_mclk_enable()
492 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); in va_macro_mclk_event()
497 return clk_prepare_enable(va->fsgen); in va_macro_mclk_event()
499 clk_disable_unprepare(va->fsgen); in va_macro_mclk_event()
511 snd_soc_dapm_to_component(widget->dapm); in va_macro_put_dec_enum()
512 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in va_macro_put_dec_enum()
516 val = ucontrol->value.enumerated.item[0]; in va_macro_put_dec_enum()
518 switch (e->reg) { in va_macro_put_dec_enum()
532 dev_err(component->dev, "%s: e->reg: 0x%x not expected\n", in va_macro_put_dec_enum()
533 __func__, e->reg); in va_macro_put_dec_enum()
534 return -EINVAL; in va_macro_put_dec_enum()
551 snd_soc_dapm_to_component(widget->dapm); in va_macro_tx_mixer_get()
553 (struct soc_mixer_control *)kcontrol->private_value; in va_macro_tx_mixer_get()
554 u32 dai_id = widget->shift; in va_macro_tx_mixer_get()
555 u32 dec_id = mc->shift; in va_macro_tx_mixer_get()
558 if (test_bit(dec_id, &va->active_ch_mask[dai_id])) in va_macro_tx_mixer_get()
559 ucontrol->value.integer.value[0] = 1; in va_macro_tx_mixer_get()
561 ucontrol->value.integer.value[0] = 0; in va_macro_tx_mixer_get()
572 snd_soc_dapm_to_component(widget->dapm); in va_macro_tx_mixer_put()
575 (struct soc_mixer_control *)kcontrol->private_value; in va_macro_tx_mixer_put()
576 u32 dai_id = widget->shift; in va_macro_tx_mixer_put()
577 u32 dec_id = mc->shift; in va_macro_tx_mixer_put()
578 u32 enable = ucontrol->value.integer.value[0]; in va_macro_tx_mixer_put()
582 set_bit(dec_id, &va->active_ch_mask[dai_id]); in va_macro_tx_mixer_put()
583 va->active_ch_cnt[dai_id]++; in va_macro_tx_mixer_put()
585 clear_bit(dec_id, &va->active_ch_mask[dai_id]); in va_macro_tx_mixer_put()
586 va->active_ch_cnt[dai_id]--; in va_macro_tx_mixer_put()
589 snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update); in va_macro_tx_mixer_put()
607 dmic_clk_cnt = &(va->dmic_0_1_clk_cnt); in va_dmic_clk_enable()
608 dmic_clk_div = &(va->dmic_0_1_clk_div); in va_dmic_clk_enable()
614 dmic_clk_cnt = &(va->dmic_2_3_clk_cnt); in va_dmic_clk_enable()
615 dmic_clk_div = &(va->dmic_2_3_clk_div); in va_dmic_clk_enable()
621 dmic_clk_cnt = &(va->dmic_4_5_clk_cnt); in va_dmic_clk_enable()
622 dmic_clk_div = &(va->dmic_4_5_clk_div); in va_dmic_clk_enable()
628 dmic_clk_cnt = &(va->dmic_6_7_clk_cnt); in va_dmic_clk_enable()
629 dmic_clk_div = &(va->dmic_6_7_clk_div); in va_dmic_clk_enable()
634 dev_err(component->dev, "%s: Invalid DMIC Selection\n", in va_dmic_clk_enable()
636 return -EINVAL; in va_dmic_clk_enable()
640 clk_div = va->dmic_clk_div; in va_dmic_clk_enable()
672 (*dmic_clk_cnt)--; in va_dmic_clk_enable()
681 clk_div = va->dmic_clk_div; in va_dmic_clk_enable()
683 clk_div = va->dmic_clk_div; in va_dmic_clk_enable()
708 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); in va_macro_enable_dmic()
709 unsigned int dmic = w->shift; in va_macro_enable_dmic()
726 struct snd_soc_component *comp = snd_soc_dapm_to_component(w->dapm); in va_macro_enable_dec()
734 decimator = w->shift; in va_macro_enable_dec()
749 va->dec_mode[decimator] << CDC_VA_ADC_MODE_SHIFT); in va_macro_enable_dec()
775 * Minimum 1 clk cycle delay is required as per HW spec in va_macro_enable_dec()
791 * 6ms delay is required as per HW spec in va_macro_enable_dec()
813 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in va_macro_dec_mode_get()
814 int path = e->shift_l; in va_macro_dec_mode_get()
816 ucontrol->value.enumerated.item[0] = va->dec_mode[path]; in va_macro_dec_mode_get()
825 int value = ucontrol->value.enumerated.item[0]; in va_macro_dec_mode_put()
826 struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; in va_macro_dec_mode_put()
827 int path = e->shift_l; in va_macro_dec_mode_put()
830 va->dec_mode[path] = value; in va_macro_dec_mode_put()
840 struct snd_soc_component *component = dai->component; in va_macro_hw_params()
843 struct device *va_dev = component->dev; in va_macro_hw_params()
872 return -EINVAL; in va_macro_hw_params()
875 for_each_set_bit(decimator, &va->active_ch_mask[dai->id], in va_macro_hw_params()
889 struct snd_soc_component *component = dai->component; in va_macro_get_channel_map()
890 struct device *va_dev = component->dev; in va_macro_get_channel_map()
893 switch (dai->id) { in va_macro_get_channel_map()
897 *tx_slot = va->active_ch_mask[dai->id]; in va_macro_get_channel_map()
898 *tx_num = va->active_ch_cnt[dai->id]; in va_macro_get_channel_map()
909 struct snd_soc_component *component = dai->component; in va_macro_digital_mute()
913 for_each_set_bit(decimator, &va->active_ch_mask[dai->id], in va_macro_digital_mute()
1120 SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micb", 0, 0),
1175 SND_SOC_DAPM_MUX_E("VA DEC0 MUX", SND_SOC_NOPM, VA_MACRO_DEC0, 0,
1180 SND_SOC_DAPM_MUX_E("VA DEC1 MUX", SND_SOC_NOPM, VA_MACRO_DEC1, 0,
1185 SND_SOC_DAPM_MUX_E("VA DEC2 MUX", SND_SOC_NOPM, VA_MACRO_DEC2, 0,
1190 SND_SOC_DAPM_MUX_E("VA DEC3 MUX", SND_SOC_NOPM, VA_MACRO_DEC3, 0,
1195 SND_SOC_DAPM_SUPPLY_S("VA_MCLK", -1, SND_SOC_NOPM, 0, 0,
1209 {"VA_AIF1_CAP Mixer", "DEC0", "VA DEC0 MUX"},
1210 {"VA_AIF1_CAP Mixer", "DEC1", "VA DEC1 MUX"},
1211 {"VA_AIF1_CAP Mixer", "DEC2", "VA DEC2 MUX"},
1212 {"VA_AIF1_CAP Mixer", "DEC3", "VA DEC3 MUX"},
1214 {"VA_AIF2_CAP Mixer", "DEC0", "VA DEC0 MUX"},
1215 {"VA_AIF2_CAP Mixer", "DEC1", "VA DEC1 MUX"},
1216 {"VA_AIF2_CAP Mixer", "DEC2", "VA DEC2 MUX"},
1217 {"VA_AIF2_CAP Mixer", "DEC3", "VA DEC3 MUX"},
1219 {"VA_AIF3_CAP Mixer", "DEC0", "VA DEC0 MUX"},
1220 {"VA_AIF3_CAP Mixer", "DEC1", "VA DEC1 MUX"},
1221 {"VA_AIF3_CAP Mixer", "DEC2", "VA DEC2 MUX"},
1222 {"VA_AIF3_CAP Mixer", "DEC3", "VA DEC3 MUX"},
1224 {"VA DEC0 MUX", "VA_DMIC", "VA DMIC MUX0"},
1234 {"VA DEC1 MUX", "VA_DMIC", "VA DMIC MUX1"},
1244 {"VA DEC2 MUX", "VA_DMIC", "VA DMIC MUX2"},
1254 {"VA DEC3 MUX", "VA_DMIC", "VA DMIC MUX3"},
1291 -84, 40, digital_gain),
1293 -84, 40, digital_gain),
1295 -84, 40, digital_gain),
1297 -84, 40, digital_gain),
1313 snd_soc_component_init_regmap(component, va->regmap); in va_macro_component_probe()
1332 struct regmap *regmap = va->regmap; in fsgen_gate_enable()
1336 if (va->has_swr_master) in fsgen_gate_enable()
1346 struct regmap *regmap = va->regmap; in fsgen_gate_disable()
1348 if (va->has_swr_master) in fsgen_gate_disable()
1360 regmap_read(va->regmap, CDC_VA_TOP_CSR_TOP_CFG0, &val); in fsgen_gate_is_enabled()
1373 struct clk *parent = va->mclk; in va_macro_register_fsgen_output()
1374 struct device *dev = va->dev; in va_macro_register_fsgen_output()
1375 struct device_node *np = dev->of_node; in va_macro_register_fsgen_output()
1383 of_property_read_string(np, "clock-output-names", &clk_name); in va_macro_register_fsgen_output()
1390 va->hw.init = &init; in va_macro_register_fsgen_output()
1391 ret = devm_clk_hw_register(va->dev, &va->hw); in va_macro_register_fsgen_output()
1395 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, &va->hw); in va_macro_register_fsgen_output()
1411 va->dmic_clk_div = VA_MACRO_CLK_DIV_2; in va_macro_validate_dmic_sample_rate()
1414 va->dmic_clk_div = VA_MACRO_CLK_DIV_3; in va_macro_validate_dmic_sample_rate()
1417 va->dmic_clk_div = VA_MACRO_CLK_DIV_4; in va_macro_validate_dmic_sample_rate()
1420 va->dmic_clk_div = VA_MACRO_CLK_DIV_6; in va_macro_validate_dmic_sample_rate()
1423 va->dmic_clk_div = VA_MACRO_CLK_DIV_8; in va_macro_validate_dmic_sample_rate()
1426 va->dmic_clk_div = VA_MACRO_CLK_DIV_16; in va_macro_validate_dmic_sample_rate()
1436 dev_err(va->dev, "%s: Invalid rate %d, for mclk %d\n", in va_macro_validate_dmic_sample_rate()
1445 struct device *dev = &pdev->dev; in va_macro_probe()
1454 return -ENOMEM; in va_macro_probe()
1456 va->dev = dev; in va_macro_probe()
1458 va->macro = devm_clk_get_optional(dev, "macro"); in va_macro_probe()
1459 if (IS_ERR(va->macro)) in va_macro_probe()
1460 return dev_err_probe(dev, PTR_ERR(va->macro), "unable to get macro clock\n"); in va_macro_probe()
1462 va->dcodec = devm_clk_get_optional(dev, "dcodec"); in va_macro_probe()
1463 if (IS_ERR(va->dcodec)) in va_macro_probe()
1464 return dev_err_probe(dev, PTR_ERR(va->dcodec), "unable to get dcodec clock\n"); in va_macro_probe()
1466 va->mclk = devm_clk_get(dev, "mclk"); in va_macro_probe()
1467 if (IS_ERR(va->mclk)) in va_macro_probe()
1468 return dev_err_probe(dev, PTR_ERR(va->mclk), "unable to get mclk clock\n"); in va_macro_probe()
1470 va->pds = lpass_macro_pds_init(dev); in va_macro_probe()
1471 if (IS_ERR(va->pds)) in va_macro_probe()
1472 return PTR_ERR(va->pds); in va_macro_probe()
1474 ret = of_property_read_u32(dev->of_node, "qcom,dmic-sample-rate", in va_macro_probe()
1477 dev_err(dev, "qcom,dmic-sample-rate dt entry missing\n"); in va_macro_probe()
1478 va->dmic_clk_div = VA_MACRO_CLK_DIV_2; in va_macro_probe()
1482 ret = -EINVAL; in va_macro_probe()
1493 va->regmap = devm_regmap_init_mmio(dev, base, &va_regmap_config); in va_macro_probe()
1494 if (IS_ERR(va->regmap)) { in va_macro_probe()
1495 ret = -EINVAL; in va_macro_probe()
1502 va->has_swr_master = data->has_swr_master; in va_macro_probe()
1505 clk_set_rate(va->mclk, 2 * VA_MACRO_MCLK_FREQ); in va_macro_probe()
1507 ret = clk_prepare_enable(va->macro); in va_macro_probe()
1511 ret = clk_prepare_enable(va->dcodec); in va_macro_probe()
1515 ret = clk_prepare_enable(va->mclk); in va_macro_probe()
1519 if (va->has_swr_master) { in va_macro_probe()
1521 regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL0, in va_macro_probe()
1524 regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL1, in va_macro_probe()
1527 regmap_update_bits(va->regmap, CDC_VA_TOP_CSR_SWR_MIC_CTL2, in va_macro_probe()
1533 if (va->has_swr_master) { in va_macro_probe()
1534 regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL, in va_macro_probe()
1536 regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL, in va_macro_probe()
1538 regmap_update_bits(va->regmap, CDC_VA_CLK_RST_CTRL_SWR_CONTROL, in va_macro_probe()
1558 va->fsgen = clk_hw_get_clk(&va->hw, "fsgen"); in va_macro_probe()
1559 if (IS_ERR(va->fsgen)) { in va_macro_probe()
1560 ret = PTR_ERR(va->fsgen); in va_macro_probe()
1567 clk_disable_unprepare(va->mclk); in va_macro_probe()
1569 clk_disable_unprepare(va->dcodec); in va_macro_probe()
1571 clk_disable_unprepare(va->macro); in va_macro_probe()
1573 lpass_macro_pds_exit(va->pds); in va_macro_probe()
1580 struct va_macro *va = dev_get_drvdata(&pdev->dev); in va_macro_remove()
1582 clk_disable_unprepare(va->mclk); in va_macro_remove()
1583 clk_disable_unprepare(va->dcodec); in va_macro_remove()
1584 clk_disable_unprepare(va->macro); in va_macro_remove()
1586 lpass_macro_pds_exit(va->pds); in va_macro_remove()
1593 regcache_cache_only(va->regmap, true); in va_macro_runtime_suspend()
1594 regcache_mark_dirty(va->regmap); in va_macro_runtime_suspend()
1596 clk_disable_unprepare(va->mclk); in va_macro_runtime_suspend()
1606 ret = clk_prepare_enable(va->mclk); in va_macro_runtime_resume()
1608 dev_err(va->dev, "unable to prepare mclk\n"); in va_macro_runtime_resume()
1612 regcache_cache_only(va->regmap, false); in va_macro_runtime_resume()
1613 regcache_sync(va->regmap); in va_macro_runtime_resume()
1624 { .compatible = "qcom,sc7280-lpass-va-macro", .data = &sm8250_va_data },
1625 { .compatible = "qcom,sm8250-lpass-va-macro", .data = &sm8250_va_data },
1626 { .compatible = "qcom,sm8450-lpass-va-macro", .data = &sm8450_va_data },
1627 { .compatible = "qcom,sc8280xp-lpass-va-macro", .data = &sm8450_va_data },