| /openbmc/qemu/tests/qtest/libqos/ |
| H A D | ahci.c | 2 * libqos AHCI functions
28 #include "ahci.h"
29 #include "pci-pc.h"
31 #include "qemu/host-utils.h"
86 uint8_t port; member
104 uint64_t ahci_alloc(AHCIQState *ahci, size_t bytes) in ahci_alloc() argument
106 g_assert(ahci); in ahci_alloc()
107 g_assert(ahci->parent); in ahci_alloc()
108 return qmalloc(ahci->parent, bytes); in ahci_alloc()
111 void ahci_free(AHCIQState *ahci, uint64_t addr) in ahci_free() argument
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| H A D | ahci.h | 5 * AHCI qtest library functions and definitions
30 #include "malloc-pc.h"
40 /*** Recognized AHCI Device Types ***/
44 /*** AHCI/HBA Register Offsets and Bitmasks ***/
106 /*** Port Memory Offsets & Bitmasks ***/
308 /* AHCI Command Header Flags & Masks*/
320 #define ATA_DEVICE_MAGIC 0xA0 /* used in ata1-3 */
344 AHCIPortQState port[32]; member
358 * Register device-to-host FIS structure.
380 * Register device-to-host FIS structure;
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| /openbmc/qemu/tests/qtest/ |
| H A D | ahci-test.c | 2 * AHCI test cases
29 #include "libqos/libqos-pc.h"
30 #include "libqos/ahci.h"
31 #include "libqos/pci-pc.h"
34 #include "qemu/host-utils.h"
52 static void ahci_test_port_spec(AHCIQState *ahci, uint8_t port);
53 static void ahci_test_pci_spec(AHCIQState *ahci);
54 static void ahci_test_pci_caps(AHCIQState *ahci, uint16_t header,
56 static void ahci_test_satacap(AHCIQState *ahci, uint8_t offset);
57 static void ahci_test_msicap(AHCIQState *ahci, uint8_t offset);
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| /openbmc/qemu/hw/ide/ |
| H A D | trace-events | 16 ide_cancel_dma_sync_buffered(void *fn, void *req) "invoking cb %p of buffered request %p with -ECAN…
65 # ahci.c
66 ahci_port_read(void *s, int port, const char *reg, int offset, uint32_t ret) "ahci(%p)[%d]: port re…
67 ahci_port_read_default(void *s, int port, const char *reg, int offset) "ahci(%p)[%d]: unimplemented…
68 ahci_irq_raise(void *s) "ahci(%p): raise irq"
69 ahci_irq_lower(void *s) "ahci(%p): lower irq"
70 ahci_check_irq(void *s, uint32_t old, uint32_t new) "ahci(%p): check irq 0x%08x --> 0x%08x"
71 …int port, const char *name, uint32_t val, uint32_t old, uint32_t new, uint32_t effective) "ahci(%p…
72 ahci_port_write(void *s, int port, const char *reg, int offset, uint32_t val) "ahci(%p)[%d]: port w…
73 …hci_port_write_unimpl(void *s, int port, const char *reg, int offset, uint32_t val) "ahci(%p)[%d]:…
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| H A D | ahci.c | 2 * QEMU AHCI Emulation
28 #include "hw/qdev-properties.h"
31 #include "qemu/error-report.h"
33 #include "qemu/main-loop.h"
35 #include "sysemu/block-backend.h"
38 #include "hw/ide/ahci-pci.h"
39 #include "hw/ide/ahci-sysbus.h"
40 #include "ahci-internal.h"
41 #include "ide-internal.h"
45 static void check_cmd(AHCIState *s, int port);
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| H A D | ich.c | 21 * lspci dump of a ICH-9 real device
23 …l Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [8086:2922] (rev 02) (prog-i…
24 …* Subsystem: Intel Corporation 82801IR/IO/IH (ICH9R/DO/DH) 6 port SATA AHCI Controller [80…
25 …* Control: I/O+ Mem+ BusMaster+ SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- Fast…
26 …* Status: Cap+ 66MHz+ UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR…
34 * Region 5: Memory at febf9000 (32-bit, non-prefetchable) [size=2K]
35 * Capabilities: [80] Message Signalled Interrupts: Mask- 64bit- Count=1/16 Enable+
38 * Flags: PMEClk- DSI- D1- D2- AuxCurrent=0mA PME(D0-,D1-,D2-,D3hot+,D3cold-)
39 * Status: D0 PME-Enable- DSel=0 DScale=0 PME-
42 * Kernel driver in use: ahci
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| /openbmc/linux/Documentation/devicetree/bindings/ata/ |
| H A D | ahci-platform.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-platform.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: AHCI SATA Controller
10 SATA nodes are defined to describe on-chip Serial ATA controllers.
13 It is possible, but not required, to represent each port as a sub-node.
14 It allows to enable each port independently when dealing with multiple
18 - Hans de Goede <hdegoede@redhat.com>
19 - Jens Axboe <axboe@kernel.dk>
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| H A D | ahci-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Common Properties for Serial ATA AHCI controllers
10 - Hans de Goede <hdegoede@redhat.com>
11 - Damien Le Moal <dlemoal@kernel.org>
14 This document defines device tree properties for a common AHCI SATA
18 document doesn't constitute a DT-node binding by itself but merely
19 defines a set of common properties for the AHCI-compatible devices.
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| H A D | rockchip,dwc-ahci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller for Rockchip devices
10 - Serge Semin <fancer.lancer@gmail.com>
14 implementation of the AHCI SATA controller found in Rockchip
22 - rockchip,rk3568-dwc-ahci
23 - rockchip,rk3588-dwc-ahci
25 - compatible
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| H A D | snps,dwc-ahci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller
10 - Serge Semin <fancer.lancer@gmail.com>
14 implementation of the AHCI SATA controller.
20 - snps,dwc-ahci
21 - snps,spear-ahci
23 - compatible
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| H A D | snps,dwc-ahci-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Synopsys DWC AHCI SATA controller properties
10 - Serge Semin <fancer.lancer@gmail.com>
14 AHCI controller properties.
19 - $ref: ahci-common.yaml#
30 Basic DWC AHCI SATA clock sources like application AXI/AHB BIU clock,
31 PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx)
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| H A D | baikal,bt1-ahci.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/baikal,bt1-ahci.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Baikal-T1 SoC AHCI SATA controller
10 - Serge Semin <fancer.lancer@gmail.com>
13 AHCI SATA controller embedded into the Baikal-T1 SoC is based on the
14 DWC AHCI SATA v4.10a IP-core.
17 - $ref: snps,dwc-ahci-common.yaml#
21 const: baikal,bt1-ahci
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| H A D | brcm,sata-brcm.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/brcm,sata-brcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Broadcom SATA3 AHCI Controller
10 SATA nodes are defined to describe on-chip Serial ATA controllers.
14 - Florian Fainelli <f.fainelli@gmail.com>
17 - $ref: ahci-common.yaml#
22 - items:
23 - enum:
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| H A D | ceva,ahci-1v84.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ata/ceva,ahci-1v84.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Ceva AHCI SATA Controller
10 - Piyush Mehta <piyush.mehta@amd.com>
13 The Ceva SATA controller mostly conforms to the AHCI interface with some
14 special extensions to add functionality, is a high-performance dual-port
15 SATA host controller with an AHCI compliant command layer which supports
17 structure (FIS) based switching for systems employing port multipliers.
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| H A D | sata_highbank.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Calxeda AHCI SATA Controller
10 The Calxeda SATA controller mostly conforms to the AHCI interface
15 - Andre Przywara <andre.przywara@arm.com>
19 const: calxeda,hb-ahci
27 dma-coherent: true
29 calxeda,pre-clocks:
35 calxeda,post-clocks:
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| /openbmc/linux/drivers/ata/ |
| H A D | ahci_platform.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AHCI SATA platform driver
5 * Copyright 2004-2005 Red Hat, Inc.
21 #include "ahci.h"
23 #define DRV_NAME "ahci"
45 struct device *dev = &pdev->dev; in ahci_probe()
47 const struct ata_port_info *port; in ahci_probe() local
59 if (device_is_compatible(dev, "hisilicon,hisi-ahci")) in ahci_probe()
60 hpriv->flags |= AHCI_HFLAG_NO_FBS | AHCI_HFLAG_NO_NCQ; in ahci_probe()
62 port = device_get_match_data(dev); in ahci_probe()
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| H A D | libahci_platform.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * AHCI SATA platform library
5 * Copyright 2004-2005 Red Hat, Inc.
26 #include "ahci.h"
37 * ahci_platform_enable_phys - Enable PHYs
40 * This function enables all the PHYs found in hpriv->phys, if any.
51 for (i = 0; i < hpriv->nports; i++) { in ahci_platform_enable_phys()
52 rc = phy_init(hpriv->phys[i]); in ahci_platform_enable_phys()
56 rc = phy_set_mode(hpriv->phys[i], PHY_MODE_SATA); in ahci_platform_enable_phys()
58 phy_exit(hpriv->phys[i]); in ahci_platform_enable_phys()
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| H A D | ahci.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * ahci.c - AHCI SATA support
6 * Please ALWAYS copy linux-ide@vger.kernel.org
9 * Copyright 2004-2005 Red Hat, Inc.
12 * as Documentation/driver-api/libata.rst
14 * AHCI hardware documentation:
25 #include <linux/dma-mapping.h>
32 #include <linux/ahci-remap.h>
33 #include <linux/io-64-nonatomic-lo-hi.h>
34 #include "ahci.h"
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| H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0
10 uses pata-platform driver to enable the relevant driver in the
21 If you want to use an ATA hard disk, ATA tape drive, ATA CD-ROM or
62 <file:Documentation/admin-guide/kernel-parameters.txt>.
76 This option adds support for ATA-related ACPI objects.
98 bool "SATA Port Multiplier support"
102 This option adds support for SATA Port Multipliers
107 comment "Controllers with non-SFF native interface"
110 tristate "AHCI SATA support"
114 This option enables support for AHCI Serial ATA.
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| H A D | acard-ahci.c | 1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * acard-ahci.c - ACard AHCI SATA support
7 * Please ALWAYS copy linux-ide@vger.kernel.org
13 * as Documentation/driver-api/libata.rst
15 * AHCI hardware documentation:
26 #include <linux/dma-mapping.h>
33 #include "ahci.h"
35 #define DRV_NAME "acard-ahci"
70 AHCI_SHT("acard-ahci"),
115 struct ahci_host_priv *hpriv = host->private_data; in acard_ahci_pci_device_suspend()
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| H A D | ahci_mvebu.c | 2 * AHCI glue platform driver for Marvell EBU SOCs
6 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
20 #include "ahci.h"
22 #define DRV_NAME "ahci-mvebu"
42 writel(0, hpriv->mmio + AHCI_WINDOW_CTRL(i)); in ahci_mvebu_mbus_config()
43 writel(0, hpriv->mmio + AHCI_WINDOW_BASE(i)); in ahci_mvebu_mbus_config()
44 writel(0, hpriv->mmio + AHCI_WINDOW_SIZE(i)); in ahci_mvebu_mbus_config()
47 for (i = 0; i < dram->num_cs; i++) { in ahci_mvebu_mbus_config()
48 const struct mbus_dram_window *cs = dram->cs + i; in ahci_mvebu_mbus_config()
50 writel((cs->mbus_attr << 8) | in ahci_mvebu_mbus_config()
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| H A D | ahci_sunxi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Allwinner sunxi AHCI SATA platform driver
7 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
20 #include "ahci.h"
22 #define DRV_NAME "ahci-sunxi"
28 "Enable support for sata port multipliers, only use if you use a pmp!");
118 if (--timeout == 0) { in ahci_sunxi_phy_init()
120 return -EIO; in ahci_sunxi_phy_init()
133 if (--timeout == 0) { in ahci_sunxi_phy_init()
135 return -EIO; in ahci_sunxi_phy_init()
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| /openbmc/u-boot/doc/device-tree-bindings/ata/ |
| H A D | intel-sata.txt | 8 - compatible = "intel,pantherpoint-ahci"
9 - intel,sata-mode : string, one of:
10 "ahci" : Use AHCI mode (default)
12 "plain-ide" : Use plain IDE mode
13 - intel,sata-port-map : Which SATA ports are enabled, bit 0=enable first port,
14 bit 1=enable second port, etc.
15 - intel,sata-port0-gen3-tx : Value for the IOBP_SP0G3IR register
16 - intel,sata-port1-gen3-tx : Value for the IOBP_SP1G3IR register
19 -------
22 compatible = "intel,pantherpoint-ahci";
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| /openbmc/u-boot/include/ |
| H A D | ahci.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
35 #define HOST_VERSION 0x10 /* AHCI spec. version compliancy */
39 #define HOST_RESET (1 << 0) /* reset controller; self-clear */
41 #define HOST_AHCI_EN (1 << 31) /* AHCI enabled */
43 /* Registers for each SATA port */
50 #define PORT_CMD 0x18 /* port command */
70 #define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */
72 #define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */
76 #define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */
106 #define PORT_CMD_START (1 << 0) /* Enable port DMA engine */
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| /openbmc/u-boot/arch/x86/cpu/ivybridge/ |
| H A D | sata.c | 1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (C) 2008-2009 coresystems GmbH
8 #include <ahci.h>
27 /* Port enable */ in common_sata_init()
41 const void *blob = gd->fdt_blob; in bd82x6x_sata_init()
50 port_map = fdtdec_get_int(blob, node, "intel,sata-port-map", 0); in bd82x6x_sata_init()
54 mode = fdt_getprop(blob, node, "intel,sata-mode", NULL); in bd82x6x_sata_init()
55 if (!mode || !strcmp(mode, "ahci")) { in bd82x6x_sata_init()
58 debug("SATA: Controller in AHCI mode\n"); in bd82x6x_sata_init()
73 /* Initialize AHCI memory-mapped space */ in bd82x6x_sata_init()
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