/openbmc/linux/Documentation/devicetree/bindings/arm/ |
H A D | xilinx.yaml | 1 # SPDX-License-Identifier: GPL-2.0 3 --- 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 7 title: Xilinx Zynq Platforms 10 - Michal Simek <michal.simek@amd.com> 13 Xilinx boards with Zynq-7000 SOC or Zynq UltraScale+ MPSoC 20 - items: 21 - enum: 22 - adapteva,parallella 23 - digilent,zynq-zybo [all …]
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/openbmc/qemu/docs/system/arm/ |
H A D | xlnx-zynq.rst | 1 Xilinx Zynq board (``xilinx-zynq-a9``) 3 The Zynq 7000 family is based on the AMD SoC architecture. These products 4 integrate a feature-rich dual or single-core Arm Cortex-A9 MPCore based 8 https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/Zynq-7000-SoC-Technical-Reference-Manual 10 QEMU xilinx-zynq-a9 board supports following devices: 11 - A9 MPCORE 12 - cortex-a9 13 - GIC v1 14 - Generic timer 15 - wdt [all …]
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/openbmc/u-boot/board/xilinx/ |
H A D | Kconfig | 1 # SPDX-License-Identifier: GPL-2.0 8 string "Zynq/ZynqMP PS init file(s) location" 10 On Zynq and ZynqMP U-Boot SPL (or U-Boot proper if 14 psu_init_gpl.c on ZynqMP, ps7_init_gpl.c for Zynq-7000) 17 U-Boot contains PS init files for some boards, but each of 22 There are three ways to give a PS init file to U-Boot: 26 ps7_init_gpl.c file is located. U-Boot will build this 29 2. If you leave an empty string here, U-Boot will use 30 board/xilinx/zynq/$(CONFIG_DEFAULT_DEVICE_TREE)/ps7_init_gpl.c 31 for Zynq-7000, or [all …]
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/openbmc/u-boot/arch/arm/dts/ |
H A D | zynq-picozed.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 7 /dts-v1/; 8 #include "zynq-7000.dtsi" 11 model = "Zynq PicoZed Board"; 12 compatible = "xlnx,zynq-picozed", "xlnx,zynq-7000"; 27 u-boot,dm-pre-reloc; 32 u-boot,dm-pre-reloc; 37 u-boot,dm-pre-reloc;
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H A D | zynq-microzed.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * Copyright (C) 2013 - 2016 Xilinx, Inc. 7 /dts-v1/; 8 #include "zynq-7000.dtsi" 11 model = "Zynq MicroZED Board"; 12 compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000"; 27 stdout-path = "serial0:115200n8"; 31 compatible = "usb-nop-xceiv"; 32 #phy-cells = <0>; 37 ps-clk-frequency = <33333333>; [all …]
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H A D | zynq-cse-nor.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 7 /dts-v1/; 8 #include "zynq-7000.dtsi" 11 #address-cells = <1>; 12 #size-cells = <1>; 13 model = "Zynq CSE NOR Board"; 14 compatible = "xlnx,zynq-cse-nor", "xlnx,zynq-7000"; 26 stdout-path = "serial0:115200n8"; 32 u-boot,dm-pre-reloc; 36 compatible = "simple-bus"; [all …]
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H A D | zynq-zybo-z7.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (C) 2011 - 2015 Xilinx 6 /dts-v1/; 7 #include "zynq-7000.dtsi" 8 #include <dt-bindings/gpio/gpio.h> 12 compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000"; 28 stdout-path = "serial0:115200n8"; 31 gpio-leds { 32 compatible = "gpio-leds"; 35 label = "zynq-zybo-z7:green:ld4"; [all …]
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H A D | zynq-zed.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (C) 2011 - 2015 Xilinx 6 /dts-v1/; 7 #include "zynq-7000.dtsi" 11 compatible = "avnet,zynq-zed", "xlnx,zynq-zed", "xlnx,zynq-7000"; 27 stdout-path = "serial0:115200n8"; 31 compatible = "usb-nop-xceiv"; 32 #phy-cells = <0>; 37 ps-clk-frequency = <33333333>; 42 phy-mode = "rgmii-id"; [all …]
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H A D | zynq-dlc20-rev1.0.dts | 1 // SPDX-License-Identifier: GPL-2.0 7 /dts-v1/; 8 #include "zynq-7000.dtsi" 11 model = "Zynq DLC20 Rev1.0"; 12 compatible = "xlnx,zynq-dlc20-rev1.0", "xlnx,zynq-dlc20", 13 "xlnx,zynq-7000"; 30 stdout-path = "serial0:115200n8"; 34 compatible = "ulpi-phy"; 35 #phy-cells = <0>; 37 view-port = <0x0170>; [all …]
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H A D | zynq-zturn.dts | 1 // SPDX-License-Identifier: GPL-2.0 6 * Based on zynq-zed.dts which is: 7 * Copyright (C) 2011 - 2014 Xilinx 12 /dts-v1/; 13 /include/ "zynq-7000.dtsi" 16 model = "Zynq Z-Turn MYIR Board"; 17 compatible = "myir,zynq-zturn", "xlnx,zynq-7000"; 32 stdout-path = "serial0:115200n8"; 35 gpio-leds { 36 compatible = "gpio-leds"; [all …]
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H A D | zynq-zc770-xm011-x16.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * Copyright (C) 2013-2018 Xilinx, Inc. 7 /dts-v1/; 8 #include "zynq-7000.dtsi" 12 compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000"; 22 stdout-path = "serial0:115200n8"; 31 compatible = "usb-nop-xceiv"; 32 #phy-cells = <0>; 42 clock-frequency = <400000>; 52 num-cs = <4>; [all …]
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H A D | zynq-zc770-xm011.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * Copyright (C) 2013-2018 Xilinx, Inc. 7 /dts-v1/; 8 #include "zynq-7000.dtsi" 12 compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000"; 22 stdout-path = "serial0:115200n8"; 31 compatible = "usb-nop-xceiv"; 32 #phy-cells = <0>; 42 clock-frequency = <400000>; 52 num-cs = <4>; [all …]
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H A D | zynq-zc770-xm012.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * Copyright (C) 2013-2018 Xilinx, Inc. 7 /dts-v1/; 8 #include "zynq-7000.dtsi" 12 compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000"; 23 stdout-path = "serial0:115200n8"; 38 clock-frequency = <400000>; 48 clock-frequency = <400000>; 58 num-cs = <4>; 59 is-decoded-cs = <0>; [all …]
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H A D | zynq-zybo.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 3 * Copyright (C) 2011 - 2015 Xilinx 6 /dts-v1/; 7 #include "zynq-7000.dtsi" 11 compatible = "digilent,zynq-zybo", "xlnx,zynq-7000"; 27 stdout-path = "serial0:115200n8"; 31 #phy-cells = <0>; 32 compatible = "usb-nop-xceiv"; 33 reset-gpios = <&gpio0 46 1>; 38 ps-clk-frequency = <50000000>; [all …]
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H A D | zynq-zc770-xm013.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 7 /dts-v1/; 8 #include "zynq-7000.dtsi" 12 compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000"; 24 stdout-path = "serial0:115200n8"; 39 phy-mode = "rgmii-id"; 40 phy-handle = <ðernet_phy>; 42 ethernet_phy: ethernet-phy@7 { 44 device_type = "ethernet-phy"; 50 clock-frequency = <400000>; [all …]
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/openbmc/u-boot/doc/ |
H A D | README.zynq | 1 # SPDX-License-Identifier: GPL-2.0+ 3 # Xilinx ZYNQ U-Boot 9 This document describes the information about Xilinx Zynq U-Boot - 12 2. Zynq boards 14 Xilinx Zynq-7000 All Programmable SoCs enable extensive system level 23 - zc770-xm010 (single qspi, gem0, mmc) 24 - zc770-xm011 (8 or 16 bit nand) 25 - zc770-xm012 (nor) 26 - zc770-xm013 (dual parallel qspi, gem1) 36 Zynq has a facility to read the bootmode from the slcr bootmode register [all …]
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/openbmc/linux/arch/arm/boot/dts/xilinx/ |
H A D | zynq-zed.dts | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) 2011 - 2014 Xilinx 6 /dts-v1/; 7 #include "zynq-7000.dtsi" 11 compatible = "avnet,zynq-zed", "xlnx,zynq-zed", "xlnx,zynq-7000"; 26 stdout-path = "serial0:115200n8"; 30 compatible = "usb-nop-xceiv"; 31 #phy-cells = <0>; 36 ps-clk-frequency = <33333333>; 41 phy-mode = "rgmii-id"; [all …]
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H A D | zynq-zybo-z7.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 2 /dts-v1/; 3 #include "zynq-7000.dtsi" 4 #include <dt-bindings/gpio/gpio.h> 8 compatible = "digilent,zynq-zybo-z7", "xlnx,zynq-7000"; 22 stdout-path = "serial0:115200n8"; 25 gpio-leds { 26 compatible = "gpio-leds"; 28 led-ld4 { 29 label = "zynq-zybo-z7:green:ld4"; [all …]
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H A D | zynq-microzed.dts | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) 2011 - 2014 Xilinx 6 /dts-v1/; 7 /include/ "zynq-7000.dtsi" 11 compatible = "avnet,zynq-microzed", "xlnx,zynq-microzed", "xlnx,zynq-7000"; 25 stdout-path = "serial0:115200n8"; 29 compatible = "usb-nop-xceiv"; 30 #phy-cells = <0>; 35 ps-clk-frequency = <33333333>; 40 phy-mode = "rgmii-id"; [all …]
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H A D | zynq-zybo.dts | 1 // SPDX-License-Identifier: GPL-2.0 3 * Copyright (C) 2011 - 2014 Xilinx 6 /dts-v1/; 7 #include "zynq-7000.dtsi" 11 compatible = "digilent,zynq-zybo", "xlnx,zynq-7000"; 26 stdout-path = "serial0:115200n8"; 30 #phy-cells = <0>; 31 compatible = "usb-nop-xceiv"; 32 reset-gpios = <&gpio0 46 1>; 37 ps-clk-frequency = <50000000>; [all …]
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H A D | zynq-zc770-xm011.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * Copyright (C) 2013-2018 Xilinx, Inc. 7 /dts-v1/; 8 #include "zynq-7000.dtsi" 12 compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000"; 22 stdout-path = "serial0:115200n8"; 31 compatible = "usb-nop-xceiv"; 32 #phy-cells = <0>; 42 clock-frequency = <400000>; 52 num-cs = <4>; [all …]
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H A D | zynq-zc770-xm012.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * Copyright (C) 2013-2018 Xilinx, Inc. 7 /dts-v1/; 8 #include "zynq-7000.dtsi" 12 compatible = "xlnx,zynq-zc770-xm012", "xlnx,zynq-7000"; 23 stdout-path = "serial0:115200n8"; 38 clock-frequency = <400000>; 48 clock-frequency = <400000>; 58 num-cs = <4>; 59 is-decoded-cs = <0>;
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H A D | zynq-cc108.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 5 * (C) Copyright 2007-2018 Xilinx, Inc. 6 * (C) Copyright 2007-2013 Michal Simek 7 * (C) Copyright 2007-2012 PetaLogix Qld Pty Ltd 11 /dts-v1/; 12 /include/ "zynq-7000.dtsi" 16 compatible = "xlnx,zynq-cc108", "xlnx,zynq-7000"; 25 stdout-path = "serial0:115200n8"; 34 compatible = "usb-nop-xceiv"; 35 #phy-cells = <0>; [all …]
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H A D | zynq-zc770-xm013.dts | 1 // SPDX-License-Identifier: GPL-2.0+ 7 /dts-v1/; 8 #include "zynq-7000.dtsi" 12 compatible = "xlnx,zynq-zc770-xm013", "xlnx,zynq-7000"; 23 stdout-path = "serial0:115200n8"; 38 phy-mode = "rgmii-id"; 39 phy-handle = <ðernet_phy>; 41 ethernet_phy: ethernet-phy@7 { 43 device_type = "ethernet-phy"; 49 clock-frequency = <400000>; [all …]
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H A D | zynq-parallella.dts | 1 // SPDX-License-Identifier: GPL-2.0 5 * Derived from zynq-zed.dts: 11 /dts-v1/; 12 /include/ "zynq-7000.dtsi" 16 compatible = "adapteva,parallella", "xlnx,zynq-7000"; 30 stdout-path = "serial0:115200n8"; 35 fclk-enable = <0xf>; 36 ps-clk-frequency = <33333333>; 41 phy-mode = "rgmii-id"; 42 phy-handle = <ðernet_phy>; [all …]
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