1*6bfe3fffSMichal Simek// SPDX-License-Identifier: GPL-2.0 2*6bfe3fffSMichal Simek/* 3*6bfe3fffSMichal Simek * Copyright (C) 2018 Xilinx, Inc. 4*6bfe3fffSMichal Simek * 5*6bfe3fffSMichal Simek * Michal Simek <michal.simek@xilinx.com> 6*6bfe3fffSMichal Simek */ 7*6bfe3fffSMichal Simek/dts-v1/; 8*6bfe3fffSMichal Simek#include "zynq-7000.dtsi" 9*6bfe3fffSMichal Simek 10*6bfe3fffSMichal Simek/ { 11*6bfe3fffSMichal Simek model = "Zynq DLC20 Rev1.0"; 12*6bfe3fffSMichal Simek compatible = "xlnx,zynq-dlc20-rev1.0", "xlnx,zynq-dlc20", 13*6bfe3fffSMichal Simek "xlnx,zynq-7000"; 14*6bfe3fffSMichal Simek 15*6bfe3fffSMichal Simek aliases { 16*6bfe3fffSMichal Simek ethernet0 = &gem0; 17*6bfe3fffSMichal Simek i2c0 = &i2c0; 18*6bfe3fffSMichal Simek serial0 = &uart1; 19*6bfe3fffSMichal Simek spi0 = &qspi; 20*6bfe3fffSMichal Simek mmc0 = &sdhci0; 21*6bfe3fffSMichal Simek }; 22*6bfe3fffSMichal Simek 23*6bfe3fffSMichal Simek memory@0 { 24*6bfe3fffSMichal Simek device_type = "memory"; 25*6bfe3fffSMichal Simek reg = <0x0 0x20000000>; 26*6bfe3fffSMichal Simek }; 27*6bfe3fffSMichal Simek 28*6bfe3fffSMichal Simek chosen { 29*6bfe3fffSMichal Simek bootargs = "earlyprintk"; 30*6bfe3fffSMichal Simek stdout-path = "serial0:115200n8"; 31*6bfe3fffSMichal Simek }; 32*6bfe3fffSMichal Simek 33*6bfe3fffSMichal Simek usb_phy0: phy0@e0002000 { 34*6bfe3fffSMichal Simek compatible = "ulpi-phy"; 35*6bfe3fffSMichal Simek #phy-cells = <0>; 36*6bfe3fffSMichal Simek reg = <0xe0002000 0x1000>; 37*6bfe3fffSMichal Simek view-port = <0x0170>; 38*6bfe3fffSMichal Simek drv-vbus; 39*6bfe3fffSMichal Simek }; 40*6bfe3fffSMichal Simek}; 41*6bfe3fffSMichal Simek 42*6bfe3fffSMichal Simek&clkc { 43*6bfe3fffSMichal Simek ps-clk-frequency = <33333333>; /* U7 */ 44*6bfe3fffSMichal Simek}; 45*6bfe3fffSMichal Simek 46*6bfe3fffSMichal Simek&gem0 { 47*6bfe3fffSMichal Simek status = "okay"; /* MIO16-MIO27, MDIO MIO52/53 */ 48*6bfe3fffSMichal Simek phy-mode = "rgmii-id"; 49*6bfe3fffSMichal Simek phy-handle = <ðernet_phy>; 50*6bfe3fffSMichal Simek 51*6bfe3fffSMichal Simek ethernet_phy: ethernet-phy@7 { /* rtl8211e - U25 */ 52*6bfe3fffSMichal Simek reg = <1>; 53*6bfe3fffSMichal Simek }; 54*6bfe3fffSMichal Simek}; 55*6bfe3fffSMichal Simek 56*6bfe3fffSMichal Simek&i2c0 { 57*6bfe3fffSMichal Simek status = "okay"; /* MIO14/15 */ 58*6bfe3fffSMichal Simek clock-frequency = <400000>; 59*6bfe3fffSMichal Simek /* U46 - m24c08 */ 60*6bfe3fffSMichal Simek eeprom: eeprom@54 { 61*6bfe3fffSMichal Simek compatible = "atmel,24c08"; 62*6bfe3fffSMichal Simek reg = <0x54>; 63*6bfe3fffSMichal Simek }; 64*6bfe3fffSMichal Simek}; 65*6bfe3fffSMichal Simek 66*6bfe3fffSMichal Simek&qspi { 67*6bfe3fffSMichal Simek u-boot,dm-pre-reloc; 68*6bfe3fffSMichal Simek status = "okay"; 69*6bfe3fffSMichal Simek is-dual = <0>; 70*6bfe3fffSMichal Simek num-cs = <1>; 71*6bfe3fffSMichal Simek spi-tx-bus-width = <4>; 72*6bfe3fffSMichal Simek spi-rx-bus-width = <4>; 73*6bfe3fffSMichal Simek flash@0 { 74*6bfe3fffSMichal Simek /* Rev1.0 W25Q128FWSIG, RevC N25Q128A */ 75*6bfe3fffSMichal Simek compatible = "n25q128a11", "jedec,spi-nor"; 76*6bfe3fffSMichal Simek reg = <0x0>; 77*6bfe3fffSMichal Simek spi-tx-bus-width = <1>; 78*6bfe3fffSMichal Simek spi-rx-bus-width = <4>; 79*6bfe3fffSMichal Simek spi-max-frequency = <50000000>; 80*6bfe3fffSMichal Simek }; 81*6bfe3fffSMichal Simek}; 82*6bfe3fffSMichal Simek 83*6bfe3fffSMichal Simek&sdhci0 { 84*6bfe3fffSMichal Simek u-boot,dm-pre-reloc; 85*6bfe3fffSMichal Simek status = "okay"; /* EMMC MTFC4GACAJCN - MIO40-MIO45 */ 86*6bfe3fffSMichal Simek non-removable; 87*6bfe3fffSMichal Simek bus-width = <4>; 88*6bfe3fffSMichal Simek}; 89*6bfe3fffSMichal Simek 90*6bfe3fffSMichal Simek&uart1 { 91*6bfe3fffSMichal Simek u-boot,dm-pre-reloc; 92*6bfe3fffSMichal Simek status = "okay"; /* MIO8/9 */ 93*6bfe3fffSMichal Simek}; 94*6bfe3fffSMichal Simek 95*6bfe3fffSMichal Simek&usb0 { 96*6bfe3fffSMichal Simek status = "okay"; /* MIO28-MIO39 */ 97*6bfe3fffSMichal Simek dr_mode = "device"; 98*6bfe3fffSMichal Simek usb-phy = <&usb_phy0>; 99*6bfe3fffSMichal Simek}; 100*6bfe3fffSMichal Simek 101*6bfe3fffSMichal Simek&watchdog0 { 102*6bfe3fffSMichal Simek reset-on-timeout; 103*6bfe3fffSMichal Simek}; 104