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/openbmc/qemu/target/microblaze/
H A Dmmu.c44 t = mmu->rams[RAM_TAG][idx]; in mmu_flush_idx()
67 for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) { in mmu_change_pid()
69 t = mmu->rams[RAM_TAG][i]; in mmu_change_pid()
88 for (i = 0; i < ARRAY_SIZE(mmu->rams[RAM_TAG]); i++) { in mmu_translate()
92 t = mmu->rams[RAM_TAG][i]; in mmu_translate()
111 d = mmu->rams[RAM_DATA][i]; in mmu_translate()
195 /* Reads to HI/LO trig reads from the mmu rams. */ in mmu_read()
205 r = extract64(env->mmu.rams[rn & 1][i], ext * 32, 32); in mmu_read()
252 /* Writes to HI/LO trig writes to the mmu rams. */ in mmu_write()
264 tmp64 = env->mmu.rams[rn & 1][i]; in mmu_write()
[all …]
H A Dmachine.c26 VMSTATE_UINT64_2DARRAY(rams, MicroBlazeMMU, 2, TLB_ENTRIES),
H A Dmmu.h70 uint64_t rams[2][TLB_ENTRIES]; member
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n1/
H A Dmemory.json8 …ECC or parity) in protected CPUs RAMs. On the core, this event counts errors in the caches (includ…
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/neoverse-n2-v2/
H A Dmemory.json8 …ECC or parity) in protected CPUs RAMs. On the core, this event counts errors in the caches (includ…
/openbmc/linux/tools/perf/pmu-events/arch/arm64/ampere/emag/
H A Dmemory.json21 …t counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs",
/openbmc/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a76/
H A Dexception.json6 …t counts any correctable or uncorrectable memory error (ECC or parity) in the protected core RAMs",
/openbmc/linux/Documentation/devicetree/bindings/soc/ti/
H A Dti,pruss.yaml19 instruction RAMs, some internal peripheral modules to facilitate industrial
35 acts on a primary Data RAM (there are usually 2 Data RAMs) at its address
99 The various Data RAMs within a single PRU-ICSS unit are represented as a
/openbmc/u-boot/include/
H A Dfsl_fman.h311 u32 fmrie; /* rams interrupt enable */
320 u32 fpmrcr; /* rams control and event */
368 /* FMFP_RCR - FMan Rams Control and Event */
/openbmc/linux/arch/xtensa/variants/fsf/include/variant/
H A Dcore.h165 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
167 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
168 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/openbmc/linux/arch/arc/
H A DKconfig244 Single Cycle RAMS to store Fast Path Code
254 Single Cycle RAMS to store Fast Path Data
/openbmc/qemu/target/xtensa/core-dc232b/
H A Dcore-isa.h171 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
173 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
174 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/openbmc/qemu/target/xtensa/core-fsf/
H A Dcore-isa.h167 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
169 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
170 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/openbmc/linux/arch/xtensa/variants/test_mmuhifi_c3/include/variant/
H A Dcore.h185 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
187 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
188 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/openbmc/linux/arch/xtensa/variants/dc232b/include/variant/
H A Dcore.h172 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
174 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
175 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc232b/
H A Dcore.h170 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
172 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
173 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/openbmc/linux/drivers/misc/eeprom/
H A DKconfig5 tristate "I2C EEPROMs / RAMs / ROMs from most vendors"
/openbmc/linux/arch/powerpc/platforms/8xx/
H A DKconfig155 This microcode relocates SMC1 and SMC2 parameter RAMs at
/openbmc/qemu/target/xtensa/core-dc233c/
H A Dcore-isa.h217 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
219 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
220 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/openbmc/u-boot/arch/xtensa/include/asm/arch-dc233c/
H A Dcore.h196 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
198 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
199 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/openbmc/qemu/target/xtensa/core-dsp3400/
H A Dcore-isa.h214 #define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */
216 #define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */
217 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/openbmc/qemu/target/xtensa/core-lx106/
H A Dcore-isa.h207 #define XCHAL_NUM_INSTRAM 2 /* number of core instr. RAMs */
209 #define XCHAL_NUM_DATARAM 2 /* number of core data RAMs */
210 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/openbmc/linux/arch/xtensa/variants/dc233c/include/variant/
H A Dcore.h218 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
220 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
221 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/
/openbmc/linux/drivers/remoteproc/
H A Dkeystone_remoteproc.c242 * Custom function to translate a DSP device address (internal RAMs only) to a
243 * kernel virtual address. The DSPs can access their RAMs at either an internal
/openbmc/qemu/target/xtensa/core-test_mmuhifi_c3/
H A Dcore-isa.h242 #define XCHAL_NUM_INSTRAM 0 /* number of core instr. RAMs */
244 #define XCHAL_NUM_DATARAM 0 /* number of core data RAMs */
245 #define XCHAL_NUM_URAM 0 /* number of core unified RAMs*/

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