| /openbmc/linux/Documentation/devicetree/bindings/pinctrl/ |
| H A D | nxp,s32g2-siul2-pinctrl.yaml | 20 Every SIUL2 region has multiple register types, and here only MSCR and
33 A list of MSCR/IMCR register regions to be reserved.
34 - MSCR (Multiplexed Signal Configuration Register)
35 An MSCR register can configure the associated pin as either a GPIO pin
41 - description: MSCR registers group 0 in SIUL2_0
42 - description: MSCR registers group 1 in SIUL2_1
43 - description: MSCR registers group 2 in SIUL2_1
|
| /openbmc/u-boot/board/freescale/s32v234evb/ |
| H A D | s32v234evb.c | 53 /* set TXD - MSCR[12] PA12 */ in setup_iomux_uart()
56 /* set RXD - MSCR[11] - PA11 */ in setup_iomux_uart()
|
| /openbmc/qemu/hw/net/ |
| H A D | mcf_fec.c | 49 uint32_t mscr; member
308 s->mscr = 0; in mcf_fec_reset()
371 case 0x044: return s->mscr; in mcf_fec_read()
437 s->mscr = value & 0xfe; in mcf_fec_write()
|
| H A D | imx_fec.c | 141 return "MSCR"; in imx_eth_reg_name()
|
| /openbmc/u-boot/board/freescale/m54451evb/ |
| H A D | sbf_dram_init.S | 15 /* mscr sdram */
|
| /openbmc/u-boot/board/freescale/m54455evb/ |
| H A D | sbf_dram_init.S | 15 /* mscr sdram */
|
| /openbmc/linux/drivers/edac/ |
| H A D | cpc925_edac.c | 136 * Memory Scrub Control Register (MSCR)
867 u32 mscr; in cpc925_get_sdram_scrub_rate() local
870 mscr = __raw_readl(pdata->vbase + REG_MSCR_OFFSET); in cpc925_get_sdram_scrub_rate()
871 si = (mscr & MSCR_SI_MASK) >> MSCR_SI_SHIFT; in cpc925_get_sdram_scrub_rate()
873 edac_dbg(0, "Mem Scrub Ctrl Register 0x%x\n", mscr); in cpc925_get_sdram_scrub_rate()
875 if (((mscr & MSCR_SCRUB_MOD_MASK) != MSCR_BACKGR_SCRUB) || in cpc925_get_sdram_scrub_rate()
|
| /openbmc/u-boot/arch/arm/include/asm/arch-s32v234/ |
| H A D | ddr.h | 12 /* DDR offset in MSCR register */
|
| /openbmc/linux/drivers/net/ethernet/dlink/ |
| H A D | dl2k.c | 1504 __u16 mscr; in mii_get_media() local
1520 mscr = mii_read (dev, phy_addr, MII_CTRL1000); in mii_get_media()
1522 if (mscr & ADVERTISE_1000FULL && mssr & LPA_1000FULL) { in mii_get_media()
1526 } else if (mscr & ADVERTISE_1000HALF && mssr & LPA_1000HALF) { in mii_get_media()
1664 mscr = mii_read (dev, phy_addr, MII_CTRL1000); in mii_set_media()
1665 mscr |= MII_MSCR_CFG_ENABLE; in mii_set_media()
1666 mscr &= ~MII_MSCR_CFG_VALUE = 0; in mii_set_media()
|
| /openbmc/u-boot/arch/m68k/include/asm/ |
| H A D | fec.h | 117 u32 mscr; /* 0x44 */ member
153 u32 mscr;
|
| H A D | fsl_mcdmafec.h | 23 u32 mscr; /* 0x044 */ member
|
| /openbmc/u-boot/drivers/net/ |
| H A D | fsl_mcdmafec.c | 117 printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr); in dbg_fec_regs()
|
| H A D | mcfmii.c | 234 fecp->mscr = miispd << 1; in __mii_init()
|
| H A D | mcffec.c | 258 printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr); in dbgFecRegs()
|
| H A D | fec_mxc.c | 158 * The i.MX28 and i.MX6 types have another field in the MSCR (aka in fec_mii_setspeed()
|
| /openbmc/linux/drivers/net/phy/ |
| H A D | marvell.c | 548 int mscr; in m88e1121_config_aneg_rgmii_delays() local
551 mscr = MII_88E1121_PHY_MSCR_RX_DELAY | in m88e1121_config_aneg_rgmii_delays()
554 mscr = MII_88E1121_PHY_MSCR_RX_DELAY; in m88e1121_config_aneg_rgmii_delays()
556 mscr = MII_88E1121_PHY_MSCR_TX_DELAY; in m88e1121_config_aneg_rgmii_delays()
558 mscr = 0; in m88e1121_config_aneg_rgmii_delays()
562 MII_88E1121_PHY_MSCR_DELAY_MASK, mscr); in m88e1121_config_aneg_rgmii_delays()
|
| /openbmc/linux/drivers/pinctrl/nxp/ |
| H A D | pinctrl-s32g2.c | 714 /* MSCR pin ID ranges */
|
| /openbmc/linux/drivers/net/ethernet/freescale/ |
| H A D | fec_main.c | 2528 * The i.MX28 and i.MX6 types have another filed in the MSCR (aka in fec_enet_mii_init()
2547 /* Clear MMFR to avoid to generate MII event by writing MSCR. in fec_enet_mii_init()
2549 * - writing MSCR: in fec_enet_mii_init()
2550 * - mmfr[31:0]_not_zero & mscr[7:0]_is_zero & in fec_enet_mii_init()
2553 * - mscr[7:0]_not_zero in fec_enet_mii_init()
|