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/openbmc/linux/Documentation/devicetree/bindings/iommu/
H A Darm,smmu.yaml1 # SPDX-License-Identifier: GPL-2.0-only
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ARM System MMU Architecture Implementation
10 - Will Deacon <will@kernel.org>
11 - Robin Murphy <Robin.Murphy@arm.com>
23 pattern: "^iommu@[0-9a-f]*"
26 - description: Qcom SoCs implementing "arm,smmu-v2"
28 - enum:
29 - qcom,msm8996-smmu-v2
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/openbmc/linux/drivers/iommu/arm/arm-smmu/
H A Darm-smmu-impl.c1 // SPDX-License-Identifier: GPL-2.0-only
5 #define pr_fmt(fmt) "arm-smmu: " fmt
10 #include "arm-smmu.h"
44 /* Since we don't care for sGFAR, we can do without 64-bit accessors */
65 cs->id_base = atomic_fetch_add(smmu->num_context_banks, &context_count); in cavium_cfg_probe()
66 dev_notice(smmu->dev, "\tenabling workaround for Cavium erratum 27704\n"); in cavium_cfg_probe()
74 struct cavium_smmu *cs = container_of(smmu_domain->smmu, in cavium_init_context()
77 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S2) in cavium_init_context()
78 smmu_domain->cfg.vmid += cs->id_base; in cavium_init_context()
80 smmu_domain->cfg.asid += cs->id_base; in cavium_init_context()
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H A Darm-smmu-nvidia.c1 // SPDX-License-Identifier: GPL-2.0-only
2 // Copyright (C) 2019-2020 NVIDIA CORPORATION. All rights reserved.
12 #include "arm-smmu.h"
15 * Tegra194 has three ARM MMU-500 Instances.
18 * non-isochronous HW devices.
23 * memory client. This is necessary to allow for use-case such as seamlessly
52 return nvidia_smmu->bases[inst] + (page << smmu->pgshift); in nvidia_smmu_page()
69 for (i = 0; i < nvidia->num_instances; i++) { in nvidia_smmu_write_reg()
90 for (i = 0; i < nvidia->num_instances; i++) { in nvidia_smmu_write_reg64()
108 for (spin_cnt = TLB_SPIN_COUNT; spin_cnt > 0; spin_cnt--) { in nvidia_smmu_tlb_sync()
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H A Darm-smmu.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * - SMMUv1 and v2 implementations
11 * - Stream-matching and stream-indexing
12 * - v7/v8 long-descriptor format
13 * - Non-secure access to the SMMU
14 * - Context fault reporting
15 * - Extended Stream ID (16 bit)
18 #define pr_fmt(fmt) "arm-smmu: " fmt
24 #include <linux/dma-mapping.h>
40 #include "arm-smmu.h"
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/openbmc/u-boot/drivers/net/
H A Dsmc91111.c1 // SPDX-License-Identifier: GPL-2.0+
2 /*------------------------------------------------------------------------
4 . This is a driver for SMSC's 91C111 single-chip Ethernet device.
7 . Sysgo Real-Time Solutions, GmbH <www.elinos.com>
43 . 06/19/03 Richard Woodruff Made u-boot environment aware and added mac addr checks.
48 ----------------------------------------------------------------------------*/
57 /* Use power-down feature of the chip */
74 /*------------------------------------------------------------------------
78 -------------------------------------------------------------------------*/
107 /*------------------------------------------------------------------------
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/openbmc/linux/arch/arm/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
8 select ARCH_HAS_CPU_FINALIZE_INIT if MMU
10 select ARCH_HAS_DEBUG_VIRTUAL if MMU
22 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
23 select ARCH_HAS_STRICT_MODULE_RWX if MMU
26 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
40 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
45 select BUILDTIME_TABLE_SORT if MMU
51 select DMA_GLOBAL_POOL if !MMU
53 select DMA_NONCOHERENT_MMAP if MMU
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/openbmc/u-boot/board/freescale/mpc8536ds/
H A Dmpc8536ds.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008-2012 Freescale Semiconductor, Inc.
10 #include <asm/mmu.h>
34 setbits_be32(&gur->pmuxcr, in board_early_init_f()
40 * So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/ in board_early_init_f()
44 setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV); in board_early_init_f()
86 * Fixed sdram init -- doesn't use serial presence detect.
92 struct ccsr_ddr __iomem *ddr = &immap->im_ddr; in fixed_sdram()
95 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS; in fixed_sdram()
96 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG; in fixed_sdram()
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/openbmc/u-boot/board/renesas/MigoR/
H A Dlowlevel_init.S1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2007-2008
9 * board/MigoR/lowlevel_init.S
34 write32 MMUCR_A, MMUCR_D ! Address of MMU Control Register
50 ! 0xA507 -> timer_STOP / WDT_CLK = max
53 ! 0x5A00 -> Clear
56 ! 0xA504 -> timer_STOP / CLK = 500ms
/openbmc/linux/drivers/gpu/drm/gma500/
H A Dpsb_drv.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2007-2011, Intel Corporation.
44 * to the different groups of PowerVR 5-series chip designs
48 * PowerVR SGX535 - Poulsbo - Intel GMA 500, Intel Atom Z5xx
49 * PowerVR SGX535 - Moorestown - Intel GMA 600
50 * PowerVR SGX535 - Oaktrail - Intel GMA 600, Intel Atom Z6xx, E6xx
51 * PowerVR SGX545 - Cedartrail - Intel GMA 3600, Intel Atom D2500, N2600
52 * PowerVR SGX545 - Cedartrail - Intel GMA 3650, Intel Atom D2550, D2700,
97 * psb_spank - reset the 2D engine
123 PSB_WSGX32(dev_priv->gtt.gatt_start, PSB_CR_BIF_TWOD_REQ_BASE); in psb_spank()
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/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dicid.c1 // SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch-fsl-layerscape/fsl_icid.h>
30 out_be32(&fm->fm_bmi_common.fmbm_ppid[tbl[i].port_id - 1], in set_fman_icids()
63 printf("WARNING unable to set iommus: %s\n", fdt_strerror(ret)); in fdt_set_iommu_prop()
88 printf("WARNING could not find node %s: %s.\n", in fdt_fixup_icid_tbl()
107 return -1; in get_fman_port_icid()
116 noff = fdt_node_offset_by_compatible(blob, -1, compat); in fdt_fixup_fman_port_icid_by_compat()
118 prop = fdt_getprop(blob, noff, "cell-index", &len); in fdt_fixup_fman_port_icid_by_compat()
120 printf("WARNING missing cell-index for fman port\n"); in fdt_fixup_fman_port_icid_by_compat()
124 printf("WARNING bad cell-index size for fman port\n"); in fdt_fixup_fman_port_icid_by_compat()
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/openbmc/linux/Documentation/devicetree/bindings/cpu/
H A Didle-states.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/cpu/idle-states.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
11 - Anup Patel <anup@brainfault.org>
15 1 - Introduction
18 ARM and RISC-V systems contain HW capable of managing power consumption
19 dynamically, where cores can be put in different low-power states (ranging
22 run-time, can be specified through device tree bindings representing the
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/openbmc/u-boot/board/ms7722se/
H A Dlowlevel_init.S1 /* SPDX-License-Identifier: GPL-2.0+ */
9 * board/ms7722se/lowlevel_init.S
39 * Address of MMU Control Register
55 ! write16 RWTCSR_A, RWTCSR_D_1 /* 0xA507 -> timer_STOP/WDT_CLK=max */
58 write16 RWTCNT_A, RWTCNT_D /*0x5A00 -> Clear */
61 write16 RWTCSR_A, RWTCSR_D_2 /* 0xA504 -> timer_STOP/CLK=500ms */
/openbmc/u-boot/board/freescale/bsc9131rdb/
H A DREADME2 --------
3 - BSC9131 is integrated device that targets Femto base station market.
5 technologies with MAPLE-B2F baseband acceleration processing elements.
6 - It's MAPLE disabled personality is called 9231.
9 . Power Architecture subsystem including a e500 processor with 256-Kbyte shared
11 . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
13 Processing (MAPLE-B2F)
14 . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
20 . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
21 ECC, up to 400-MHz clock/800 MHz data rate
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/openbmc/linux/drivers/cpufreq/
H A Dpmac32-cpufreq.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2002 - 2005 Benjamin Herrenschmidt <benh@kernel.crashing.org>
41 * init/main.c to make it non-init before enabling DEBUG_FREQ
100 * core cpufreq framework's own calculation. in debug_calc_bogomips()
197 /* Delay is way too big but it's ok, we schedule */ in gpios_set_cpu_speed()
219 /* Delay is way too big but it's ok, we schedule */ in gpios_set_cpu_speed()
254 * the above didn't re-enable the DEC */ in pmu_set_cpu_speed()
270 save_l3cr = _get_L3CR(); /* (returns -1 if not available) */ in pmu_set_cpu_speed()
271 save_l2cr = _get_L2CR(); /* (returns -1 if not available) */ in pmu_set_cpu_speed()
298 /* Restore userland MMU context */ in pmu_set_cpu_speed()
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/openbmc/linux/arch/alpha/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
42 The Alpha is a 64-bit general-purpose processor designed and
44 now Hewlett-Packard. The Alpha Linux project has a home page at
50 config MMU config
91 Alcor/Alpha-XLT AS 600, AS 500, XL-300, XL-366
92 Alpha-XL XL-233, XL-266
101 Jensen DECpc 150, DEC 2000 models 300, 500
102 LX164 AlphaPC164-LX
104 Miata Personal Workstation 433/500/600 a/au
111 Ruffian RPX164-2, AlphaPC164-UX, AlphaPC164-BX
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/openbmc/u-boot/arch/arm/mach-mvebu/
H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2014-2016 Stefan Roese <sr@denx.de>
32 * on Armada to configure CP15 in start.S / cpu_init_cp15() in lowlevel_init()
41 writel(readl(&reg->rstoutn_mask) | 1, &reg->rstoutn_mask); in reset_cpu()
42 writel(readl(&reg->sys_soft_rst) | 1, &reg->sys_soft_rst); in reset_cpu()
86 { 7, 0x0, 500, 250, 250 },
87 { 8, 0x0, 500, 250, 334 },
88 { 9, 0x0, 500, 250, 500 },
104 { 25, 0x0, 1000, 500, 500 },
105 { 26, 0x0, 1000, 500, 667 },
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/openbmc/linux/drivers/gpu/drm/lima/
H A Dlima_sched.c1 // SPDX-License-Identifier: GPL-2.0 OR MIT
2 /* Copyright 2017-2019 Qiang Yu <yuq825@gmail.com> */
4 #include <linux/iosys-map.h>
34 return -ENOMEM; in lima_sched_slab_init()
43 if (!--lima_fence_slab_refcnt) { in lima_sched_slab_fini()
63 return f->pipe->base.name; in lima_fence_get_timeline_name()
78 call_rcu(&f->base.rcu, lima_fence_release_rcu); in lima_fence_release()
95 fence->pipe = pipe; in lima_fence_create()
96 dma_fence_init(&fence->base, &lima_fence_ops, &pipe->fence_lock, in lima_fence_create()
97 pipe->fence_context, ++pipe->fence_seqno); in lima_fence_create()
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/openbmc/u-boot/board/freescale/bsc9132qds/
H A DREADME2 --------
4 Microcell, Picocell, and Enterprise-Femto base station market subsegments.
7 core technologies with MAPLE-B2P baseband acceleration processing elements
15 - Power Architecture subsystem including two e500 processors with
16 512-Kbyte shared L2 cache
17 - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
19 - 32 Kbyte of shared M3 memory
20 - The Multi Accelerator Platform Engine for Pico BaseStation Baseband
21 Processing (MAPLE-B2P)
22 - Two DDR3/3L memory interfaces with 32-bit data width (40 bits including
[all …]
/openbmc/linux/arch/sparc/include/asm/
H A Dfloppy_32.h1 /* SPDX-License-Identifier: GPL-2.0 */
4 * Copyright (C) 1995 David S. Miller (davem@davemloft.net)
76 #if 0 /* P3: added by Alain, these cause a MMU corruption. 19960524 XXX */
100 #define CROSS_64KB(a,s) (0) argument
106 sun_fdc->dor_82077 = value; in sun_set_dor()
111 return sun_fdc->dir_82077; in sun_read_dir()
122 return sun_fdc->status_82072 & ~STATUS_DMA; in sun_82072_fd_inb()
124 return sun_fdc->data_82072; in sun_82072_fd_inb()
142 sun_fdc->data_82072 = value; in sun_82072_fd_outb()
145 sun_fdc->dcr_82072 = value; in sun_82072_fd_outb()
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/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc13 ---------
14 The LS1043A integrated multicore processor combines four ARM Cortex-A53
20 - Four 64-bit ARM Cortex-A53 CPUs
21 - 1 MB unified L2 Cache
22 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
24 - Data Path Acceleration Architecture (DPAA) incorporating acceleration the
26 - Packet parsing, classification, and distribution (FMan)
27 - Queue management for scheduling, packet sequencing, and congestion
29 - Hardware buffer management for buffer allocation and de-allocation (BMan)
30 - Cryptography acceleration (SEC)
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/openbmc/linux/Documentation/devicetree/bindings/misc/
H A Dfsl,qoriq-mc.txt3 The Freescale Management Complex (fsl-mc) is a hardware resource
5 network-oriented packet processing applications. After the fsl-mc
12 For an overview of the DPAA2 architecture and fsl-mc bus see:
16 same hardware "isolation context" and a 10-bit value called an ICID
21 between ICIDs and IOMMUs, so an iommu-map property is used to define
28 For arm-smmu binding, see:
32 The msi-map property is used to associate the devices with both the ITS
36 Documentation/devicetree/bindings/interrupt-controller/msi.txt.
39 Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml.
43 - compatible
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/openbmc/linux/drivers/gpu/drm/panfrost/
H A Dpanfrost_job.c1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/dma-resv.h>
25 #define JOB_TIMEOUT_MS 500
27 #define job_write(dev, reg, data) writel(data, dev->iomem + (reg))
28 #define job_read(dev, reg) readl(dev->iomem + (reg))
71 switch (f->queue) { in panfrost_fence_get_timeline_name()
73 return "panfrost-js-0"; in panfrost_fence_get_timeline_name()
75 return "panfrost-js-1"; in panfrost_fence_get_timeline_name()
77 return "panfrost-js-2"; in panfrost_fence_get_timeline_name()
91 struct panfrost_job_slot *js = pfdev->js; in panfrost_fence_create()
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/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsdx75.dtsi1 // SPDX-License-Identifier: BSD-3-Clause
9 #include <dt-bindings/clock/qcom,rpmh.h>
10 #include <dt-bindings/clock/qcom,sdx75-gcc.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/power/qcom,rpmhpd.h>
13 #include <dt-bindings/power/qcom-rpmpd.h>
14 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
17 #address-cells = <2>;
18 #size-cells = <2>;
19 interrupt-parent = <&intc>;
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/openbmc/u-boot/include/configs/
H A Dmpc8308_p1m.h1 /* SPDX-License-Identifier: GPL-2.0+ */
3 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc.
19 * On-board devices
46 * in 8308's HRCWH according to the manual, but original Freescale's
131 * consist of two chips HY5PS12621BFP-C4 from HYNIX
205 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
245 #define CONFIG_SYS_FLASH_WRITE_TOUT (500 * 1024)
305 * Addresses are mapped 1-1.
346 /* Options are: eTSEC[0-1] */
398 * MMU Setup
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/openbmc/u-boot/board/freescale/mpc8569mds/
H A Dmpc8569mds.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2009-2010 Freescale Semiconductor.
13 #include <asm/mmu.h>
30 #include "../common/pq-mds-pib.h"
139 /* UART1 is muxed with QE PortF bit [9-12].*/
188 gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK; in board_early_init_f()
189 gur->plppar1 |= PLPPAR1_I2C2_VAL; in board_early_init_f()
190 gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK; in board_early_init_f()
191 gur->plpdir1 |= PLPDIR1_I2C2_VAL; in board_early_init_f()
205 * Remap Boot flash to caching-inhibited in board_early_init_r()
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