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/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr2.yaml4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
7 title: LPDDR2 SDRAM compliant to JEDEC JESD209-2
23 - jedec,lpddr2-nvm
24 - jedec,lpddr2-s2
25 - jedec,lpddr2-s4
27 - pattern: "^lpddr2-[0-9a-f]{2},[0-9a-f]{4}$"
29 - jedec,lpddr2-nvm
30 - jedec,lpddr2-s2
31 - jedec,lpddr2-s4
128 "^lpddr2-timings":
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H A Djedec,lpddr2-timings.yaml4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr2-timings.yaml#
7 title: LPDDR2 SDRAM AC timing parameters for a given speed-bin
14 const: jedec,lpddr2-timings
117 compatible = "jedec,lpddr2-timings";
H A Djedec,lpddr-channel.yaml21 - jedec,lpddr2-channel
67 const: jedec,lpddr2-channel
71 $ref: /schemas/memory-controllers/ddr/jedec,lpddr2.yaml#
/openbmc/u-boot/board/freescale/mx6memcal/
H A DKconfig88 Select the type of DDR (DDR3 or LPDDR2) used on your design
95 config LPDDR2 config in mx6memcal specifics""choicec87005010304
96 bool "LPDDR2"
98 Select this if your board design uses LPDDR2.
122 bool "Micron MT42L256M32D2LG LPDDR2 256Mx32 (1GiB/chip)"
123 depends on LPDDR2
126 bool "Micron MT29PZZZ4D4BKESK multi-chip 512MiB LPDDR2/4GiB eMMC"
127 depends on LPDDR2
H A DREADME35 4. The type of DDR (DDR3 or LPDDR2). Note that LPDDR2 support
38 parts and four DDR3 and two LPDDR2 parts are currently defined
/openbmc/linux/arch/arm/boot/dts/ti/omap/
H A Delpida_ecb240abacn.dtsi7 elpida_ECB240ABACN: lpddr2 {
8 compatible = "elpida,ECB240ABACN","jedec,lpddr2-s4";
24 timings_elpida_ECB240ABACN_400mhz: lpddr2-timings@0 {
25 compatible = "jedec,lpddr2-timings";
46 timings_elpida_ECB240ABACN_200mhz: lpddr2-timings@1 {
47 compatible = "jedec,lpddr2-timings";
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra20-emc.yaml19 standard protocols: DDR1, LPDDR2 and DDR2.
167 lpddr2:
168 $ref: ddr/jedec,lpddr2.yaml#
180 - lpddr2
242 lpddr2 {
243 compatible = "elpida,B8132B2PB-6D-F", "jedec,lpddr2-s4";
/openbmc/linux/drivers/mtd/lpddr/
H A DKconfig2 menu "LPDDR & LPDDR2 PCM memory drivers"
25 tristate "Support for LPDDR2-NVM flash chips"
27 This option enables support of PCM memories with a LPDDR2-NVM
H A Dlpddr2_nvm.c3 * LPDDR2-NVM MTD driver. This module provides read, write, erase, lock/unlock
4 * support for LPDDR2-NVM PCM memories
54 /* LPDDR2-NVM Commands */
63 /* LPDDR2-NVM Registers offset */
131 * Enable lpddr2-nvm Overlay Window
132 * Overlay Window is a memory mapped area containing all LPDDR2-NVM registers
146 * Disable lpddr2-nvm Overlay Window
147 * Overlay Window is a memory mapped area containing all LPDDR2-NVM registers
161 * Execute lpddr2-nvm operations
231 * Execute lpddr2-nvm operations @ block level
[all …]
/openbmc/linux/Documentation/driver-api/memory-devices/
H A Dti-emif.rst30 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
31 This driver takes care of only LPDDR2 memories presently. The
63 - mr4 : last polled value of MR4 register in the LPDDR2 device. MR4
/openbmc/linux/drivers/memory/
H A Djedec_ddr.h96 * LPDDR2 related defines
143 * Structure for timings from the LPDDR2 datasheet
205 * Structure for information about LPDDR2 chip. All parameters are
221 * Structure for timings for LPDDR3 based on LPDDR2 plus additional fields.
H A Dof_memory.c96 * @device_type: Type of ddr(LPDDR2 S2/S4)
117 tim_compat = "jedec,lpddr2-timings"; in of_get_ddr_timings()
307 * of_lpddr2_get_info() - extracts information about the lpddr2 chip.
308 * @np: Pointer to device tree node containing lpddr2 info
351 if (of_device_is_compatible(np, "jedec,lpddr2-s4")) in of_lpddr2_get_info()
353 else if (of_device_is_compatible(np, "jedec,lpddr2-s2")) in of_lpddr2_get_info()
355 else if (of_device_is_compatible(np, "jedec,lpddr2-nvm")) in of_lpddr2_get_info()
H A Djedec_ddr_data.c14 /* LPDDR2 addressing details from JESD209-2 section 2.4 */
30 /* LPDDR2 AC timing parameters from JESD209-2 section 12 */
H A DKconfig97 supports one or more of DDR2, DDR3, and LPDDR2 SDRAM protocols.
98 This driver takes care of only LPDDR2 memories presently. The
/openbmc/linux/include/linux/platform_data/
H A Demif_plat.h46 * @type: Device type (LPDDR2-S4, LPDDR2-S2 etc)
80 * @temp_alert_poll_interval_ms: LPDDR2 MR4 polling interval at nominal
/openbmc/u-boot/doc/device-tree-bindings/memory-controllers/
H A Dst,stm32mp1-ddr.txt1 ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC)
26 (DDR3/LPDDR2/LPDDR3)
104 - st,phy-reg : phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
/openbmc/linux/Documentation/devicetree/bindings/memory-controllers/ti/
H A Demif.txt5 DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
24 - device-handle : phandle to a "lpddr2" node representing the memory part
/openbmc/linux/drivers/soc/atmel/
H A Dsoc.c140 "sama5d27c 128MiB LPDDR2 SiP", "sama5d2"),
143 "sama5d27c 256MiB LPDDR2 SiP", "sama5d2"),
155 "sama5d28c 128MiB LPDDR2 SiP", "sama5d2"),
158 "sama5d28c 256MiB LPDDR2 SiP", "sama5d2"),
/openbmc/u-boot/arch/arm/include/asm/arch-mx6/
H A Dmx6-ddr.h379 /* Device Information: Varies per LPDDR2 part number and speed grade */
381 u16 mem_speed; /* ie 800 for LPDDR2-800 */
409 u8 ddr_type; /* DDR type: DDR3(0) or LPDDR2(1) */
439 /* lpddr2 zq hw calibration */
/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dlpddr2.h9 /* definitions for LPDDR2 PAD values */
44 …E 0x00001688 /* WALAT=0, BI bank interleave on, LPDDR2_S2=0, MIF3=3, RALAT=2, 8 banks, LPDDR2 */
/openbmc/u-boot/drivers/ram/stm32mp1/
H A DKconfig10 family: support for LPDDR2, LPDDR3 and DDR3
/openbmc/u-boot/arch/arm/include/asm/arch-rockchip/
H A Dsdram_rk3036.h315 * 100: lpddr2-s2
316 * 101: lpddr2-s4
/openbmc/u-boot/board/freescale/s32v234evb/
H A DMakefile6 obj-y += lpddr2.o
/openbmc/u-boot/arch/arm/mach-imx/mx6/
H A Dddr.c916 * - ddr3/lpddr2 chip details
923 * 2. i.Mx6SL LPDDR2 Script Aid spreadsheet V0.04 designed to generate MMDC
939 * According JESD209-2B-LPDDR2: Table 103
965 * According JESD209-2B-LPDDR2: Table 103
1019 /* LPDDR2-S2 and LPDDR2-S4 have the same tRFC value. */ in mx6_lpddr2_cfg()
1039 * txpdll, txpr, taonpd and taofpd are not relevant in LPDDR2 mode, in mx6_lpddr2_cfg()
1049 /* tckesr for LPDDR2 */ in mx6_lpddr2_cfg()
1059 /* LPDDR2 mode use tRCD_LP filed in MDCFG3. */ in mx6_lpddr2_cfg()
1065 /* To LPDDR2, CL in MDCFG0 refers to RL */ in mx6_lpddr2_cfg()
1127 * In LPDDR2 mode this register should be cleared, in mx6_lpddr2_cfg()
[all …]
/openbmc/u-boot/board/freescale/mx6slevk/
H A Dmx6slevk.c409 .rtt_wr = 0, /* LPDDR2 does not need rtt_wr rtt_nom */ in spl_dram_init()
411 .sde_to_rst = 0, /* LPDDR2 does not need this field */ in spl_dram_init()
412 .rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */ in spl_dram_init()

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