Home
last modified time | relevance | path

Searched full:gcc_pcie_0_phy_bcr (Results 1 – 25 of 43) sorted by relevance

12

/openbmc/linux/include/dt-bindings/reset/
H A Dqcom,gcc-apq8084.h91 #define GCC_PCIE_0_PHY_BCR 82 macro
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dqcom,msm8998-qmp-pcie-phy.yaml92 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
H A Dqcom,msm8996-qmp-pcie-phy.yaml154 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
/openbmc/linux/include/dt-bindings/clock/
H A Dqcom,qdu1000-gcc.h151 #define GCC_PCIE_0_PHY_BCR 6 macro
H A Dqcom,gcc-sm6350.h166 #define GCC_PCIE_0_PHY_BCR 7 macro
H A Dqcom,gcc-qcs404.h166 #define GCC_PCIE_0_PHY_BCR 10 macro
H A Dqcom,gcc-sc7280.h210 #define GCC_PCIE_0_PHY_BCR 1 macro
H A Dqcom,sm8550-gcc.h190 #define GCC_PCIE_0_PHY_BCR 6 macro
H A Dqcom,gcc-sm8450.h206 #define GCC_PCIE_0_PHY_BCR 7 macro
H A Dqcom,gcc-sm8150.h218 #define GCC_PCIE_0_PHY_BCR 5 macro
H A Dqcom,gcc-sdm845.h229 #define GCC_PCIE_0_PHY_BCR 24 macro
H A Dqcom,gcc-sm8350.h221 #define GCC_PCIE_0_PHY_BCR 7 macro
H A Dqcom,gcc-sm8250.h219 #define GCC_PCIE_0_PHY_BCR 7 macro
H A Dqcom,gcc-msm8998.h277 #define GCC_PCIE_0_PHY_BCR 76 macro
H A Dqcom,gcc-sc8180x.h258 #define GCC_PCIE_0_PHY_BCR 5 macro
H A Dqcom,sa8775p-gcc.h272 #define GCC_PCIE_0_PHY_BCR 10 macro
H A Dqcom,gcc-msm8996.h320 #define GCC_PCIE_0_PHY_BCR 80 macro
H A Dqcom,gcc-sc8280xp.h406 #define GCC_PCIE_0_PHY_BCR 4 macro
/openbmc/linux/drivers/clk/qcom/
H A Dgcc-qdu1000.c2596 [GCC_PCIE_0_PHY_BCR] = { 0x7c000 },
H A Dgcc-qcs404.c2778 [GCC_PCIE_0_PHY_BCR] = { 0x3e004 },
H A Dgcc-sm8450.c3178 [GCC_PCIE_0_PHY_BCR] = { 0x7c01c },
H A Dgcc-sc7280.c3387 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
H A Dgcc-sm8250.c3543 [GCC_PCIE_0_PHY_BCR] = { 0x6c01c },
/openbmc/linux/arch/arm64/boot/dts/qcom/
H A Dsa8775p.dtsi2497 resets = <&gcc GCC_PCIE_0_PHY_BCR>;
H A Dmsm8998.dtsi989 resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;

12