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/openbmc/linux/drivers/cpufreq/
H A Dlongrun.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (C) 2002 - 2003 Dominik Brodowski <linux@brodo.de>
23 * performance_pctg = (current_freq - low_freq)/(high_freq - low_freq)
29 * longrun_get_policy - get the current LongRun policy
40 pr_debug("longrun flags are %x - %x\n", msr_lo, msr_hi); in longrun_get_policy()
42 policy->policy = CPUFREQ_POLICY_PERFORMANCE; in longrun_get_policy()
44 policy->policy = CPUFREQ_POLICY_POWERSAVE; in longrun_get_policy()
47 pr_debug("longrun ctrl is %x - %x\n", msr_lo, msr_hi); in longrun_get_policy()
53 policy->min = policy->max = longrun_high_freq; in longrun_get_policy()
55 policy->min = longrun_low_freq + msr_lo * in longrun_get_policy()
[all …]
H A Dpowernow-k8.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * (c) 2003-2006 Advanced Micro Devices, Inc.
9 u32 numps; /* number of p-states */
10 u32 batps; /* number of p-states supported on battery */
13 * vid/fid pairings, but are modified during the ->target() call
36 * handle hotplug events - so just point at cpufreq pol->cpus
53 /* Model Specific Registers for p-state transitions. MSRs are 64-bit. For */
54 /* writes (wrmsr - opcode 0f 30), the register number is placed in ecx, and */
55 /* the value to write is placed in edx:eax. For reads (rdmsr - opcode 0f 32), */
56 /* the register number is placed in ecx, and the data is returned in edx:eax. */
[all …]
H A Dpowernow-k7.c1 // SPDX-License-Identifier: GPL-2.0-only
10 * - We cli/sti on stepping A0 CPUs around the FID/VID transition.
13 * - We disable half multipliers if ACPI is used on A0 stepping CPUs.
38 #include "powernow-k7.h"
69 /* divide by 1000 to get VCore voltage in V. */
74 1075, 1050, 1025, 1000, 975, 950, 925, 0,
82 150, 225, 160, 165, 170, 180, -1, -1,
95 static unsigned int minimum_speed = -1;
105 unsigned int f = fsb / 1000; in check_fsb()
107 delta = (fsbspeed > f) ? fsbspeed - f : f - fsbspeed; in check_fsb()
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H A Dpowernow-k8.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * (c) 2003-2012 Advanced Micro Devices, Inc.
8 * Based on the powernow-k7.c module written by Dave Jones.
48 #include "powernow-k8.h"
66 return 1000 * find_freq_from_fid(fid); in find_khz_freq_from_fid()
112 data->currvid = hi & MSR_S_HI_CURRENT_VID; in query_current_values_with_pending_wait()
113 data->currfid = lo & MSR_S_LO_CURRENT_FID; in query_current_values_with_pending_wait()
121 udelay((1 << data->irt) * 10); in count_off_irt()
127 udelay(data->vstable * VST_UNITS_20US); in count_off_vst()
149 u32 savevid = data->currvid; in write_new_fid()
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/openbmc/linux/arch/x86/kernel/cpu/
H A Dvmware.c20 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
56 #define STEALCLOCK_NOT_AVAILABLE (-1)
60 #define VMWARE_PORT(cmd, eax, ebx, ecx, edx) \ argument
62 "=a"(eax), "=c"(ecx), "=d"(edx), "=b"(ebx) : \
68 #define VMWARE_VMCALL(cmd, eax, ebx, ecx, edx) \ argument
70 "=a"(eax), "=c"(ecx), "=d"(edx), "=b"(ebx) : \
76 #define VMWARE_VMMCALL(cmd, eax, ebx, ecx, edx) \ argument
78 "=a"(eax), "=c"(ecx), "=d"(edx), "=b"(ebx) : \
84 #define VMWARE_CMD(cmd, eax, ebx, ecx, edx) do { \ argument
87 VMWARE_VMCALL(cmd, eax, ebx, ecx, edx); \
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/openbmc/linux/Documentation/devicetree/bindings/arm/
H A Dcalxeda.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Rob Herring <robh@kernel.org>
12 Bindings for boards with Calxeda Cortex-A9 based ECX-1000 (Highbank) SOC
13 or Cortex-A15 based ECX-2000 SOCs
20 - enum:
21 - calxeda,highbank
22 - calxeda,ecx-2000
/openbmc/qemu/docs/system/arm/
H A Dhighbank.rst4 ``highbank`` is a model of the Calxeda Highbank (ECX-1000) system,
5 which has four Cortex-A9 cores.
7 ``midway`` is a model of the Calxeda Midway (ECX-2000) system,
8 which has four Cortex-A15 cores.
12 - L2x0 cache controller
13 - SP804 dual timer
14 - PL011 UART
15 - PL061 GPIOs
16 - PL031 RTC
17 - PL022 synchronous serial port controller
[all …]
/openbmc/linux/arch/arm/mach-highbank/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
3 bool "Calxeda ECX-1000/2000 (Highbank/Midway)"
/openbmc/qemu/target/i386/hvf/
H A Dhvf.c50 #include "qemu/error-report.h"
59 #include "hvf-i386.h"
75 #include "qemu/main-loop.h"
85 int tpr = cpu_get_apic_tpr(x86_cpu->apic_state) << 4; in vmx_update_tpr()
86 int irr = apic_get_highest_priority_irr(x86_cpu->apic_state); in vmx_update_tpr()
88 wreg(cpu->accel->fd, HV_X86_TPR, tpr); in vmx_update_tpr()
89 if (irr == -1) { in vmx_update_tpr()
90 wvmcs(cpu->accel->fd, VMCS_TPR_THRESHOLD, 0); in vmx_update_tpr()
92 wvmcs(cpu->accel->fd, VMCS_TPR_THRESHOLD, (irr > tpr) ? tpr >> 4 : in vmx_update_tpr()
100 int tpr = rreg(cpu->accel->fd, HV_X86_TPR) >> 4; in update_apic_tpr()
[all …]
/openbmc/linux/drivers/thermal/intel/
H A Dx86_pkg_temp_thermal.c1 // SPDX-License-Identifier: GPL-2.0-only
94 * - cpu hotplug: Read serialized by cpu hotplug lock
97 * - Other callsites: Must hold pkg_temp_lock
113 ret = intel_tcc_get_temp(zonedev->cpu, &val, true); in sys_get_curr_temp()
117 *temp = val * 1000; in sys_get_curr_temp()
129 tj_max = intel_tcc_get_tjmax(zonedev->cpu); in sys_set_trip_temp()
132 tj_max *= 1000; in sys_set_trip_temp()
134 val = (tj_max - temp)/1000; in sys_set_trip_temp()
137 return -EINVAL; in sys_set_trip_temp()
139 ret = rdmsr_on_cpu(zonedev->cpu, MSR_IA32_PACKAGE_THERM_INTERRUPT, in sys_set_trip_temp()
[all …]
H A Dintel_powerclamp.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * intel_powerclamp.c - package c-state idle injection
5 * Copyright (c) 2012-2023, Intel Corporation.
16 * cpu in non-irq context does not reduce irq. for majority of the
56 /* Idle ratio observed using package C-state counters */
91 pr_err("Out of recommended range %lu, between 6-25ms\n", in duration_set()
93 ret = -EINVAL; in duration_set()
98 duration = clamp(new_duration, 6ul, 25ul) * 1000; in duration_set()
110 ret = sysfs_emit(buf, "%d\n", duration / 1000); in duration_get()
138 return -ENOMEM; in allocate_copy_idle_injection_mask()
[all …]
/openbmc/linux/arch/x86/kernel/cpu/resctrl/
H A Dinternal.h1 /* SPDX-License-Identifier: GPL-2.0 */
15 #define CQM_LIMBOCHECK_INTERVAL 1000
18 #define MBM_OVERFLOW_INTERVAL 1000
30 #define MBM_CNTR_WIDTH_OFFSET_MAX (62 - MBM_CNTR_WIDTH_BASE)
38 /* Non-Temporal Writes to Local Memory */
41 /* Non-Temporal Writes to Remote Memory */
65 struct kernfs_fs_context *kfc = fc->fs_private; in rdt_fc2context()
74 * struct mon_evt - Entry in the event list of a resource
78 * @list: entry in &rdt_resource->evt_list
88 * union mon_data_bits - Monitoring details for each event file
[all …]
/openbmc/linux/tools/testing/selftests/x86/
H A Damx.c1 // SPDX-License-Identifier: GPL-2.0
25 # error This test is 64-bit only
108 uint32_t eax, ebx, ecx, edx; in check_cpuid_xsave() local
111 * CPUID.1:ECX.XSAVE[bit 26] enumerates general in check_cpuid_xsave()
115 __cpuid_count(1, 0, eax, ebx, ecx, edx); in check_cpuid_xsave()
116 if (!(ecx & CPUID_LEAF1_ECX_XSAVE_MASK)) in check_cpuid_xsave()
118 if (!(ecx & CPUID_LEAF1_ECX_OSXSAVE_MASK)) in check_cpuid_xsave()
136 uint32_t eax, ebx, ecx, edx; in check_cpuid_xtiledata() local
139 eax, ebx, ecx, edx); in check_cpuid_xtiledata()
151 eax, ebx, ecx, edx); in check_cpuid_xtiledata()
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/openbmc/linux/tools/power/x86/x86_energy_perf_policy/
H A Dx86_energy_perf_policy.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * x86_energy_perf_policy -- set the energy versus performance
7 * Copyright (c) 2010 - 2017 Intel Corporation.
30 #define OPTARG_NORMAL (INT_MAX - 1)
31 #define OPTARG_POWER (INT_MAX - 2)
32 #define OPTARG_BALANCE_POWER (INT_MAX - 3)
33 #define OPTARG_BALANCE_PERFORMANCE (INT_MAX - 4)
34 #define OPTARG_PERFORMANCE (INT_MAX - 5)
103 fprintf(stderr, "scope: --cpu cpu-list [--hwp-use-pkg #] | --pkg pkg-list\n"); in usage()
104 fprintf(stderr, "field: --all | --epb | --hwp-epp | --hwp-min | --hwp-max | --hwp-desired\n"); in usage()
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/openbmc/qemu/target/i386/
H A Dcpu.c23 #include "qemu/qemu-print.h"
24 #include "qemu/hw-version.h"
26 #include "tcg/helper-tcg.h"
28 #include "hvf/hvf-i386.h"
32 #include "qemu/error-report.h"
33 #include "qapi/qapi-visit-machine.h"
34 #include "standard-headers/asm-x86/kvm_para.h"
35 #include "hw/qdev-properties.h"
39 #include "qapi/qapi-commands-machine-target.h"
40 #include "exec/address-spaces.h"
[all …]
/openbmc/u-boot/arch/x86/cpu/broadwell/
H A Dcpu.c1 // SPDX-License-Identifier: GPL-2.0
94 return -ENODEV; in arch_cpu_init_dm()
142 gd->arch.pei_boot_mode = PEI_BOOT_NONE; in checkcpu()
160 * The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate
176 } while (wait_count < 1000); in pcode_ready()
178 return -ETIMEDOUT; in pcode_ready()
243 msr.hi |= (0x01 << (52 - 32)); /* PSI3 threshold - 1A */ in initialize_vr_config()
244 msr.hi |= (0x05 << (42 - 32)); /* PSI2 threshold - 5A */ in initialize_vr_config()
245 msr.hi |= (0x14 << (32 - 32)); /* PSI1 threshold - 20A */ in initialize_vr_config()
246 msr.hi |= (1 << (62 - 32)); /* Enable PSI4 */ in initialize_vr_config()
[all …]
/openbmc/linux/drivers/idle/
H A Dintel_idle.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * intel_idle.c - native hardware idle loop for modern Intel processors
5 * Copyright (c) 2013 - 2020, Intel Corporation.
23 * for preventing entry into deep C-states
25 * CPU will flush caches as needed when entering a C-state via MWAIT
33 * ACPI has a .suspend hack to turn off deep c-statees during suspend
39 /* un-commen
139 unsigned long ecx = 1*irqoff; /* break on interrupt flag */ __intel_idle() local
212 unsigned long ecx = 1; /* break on interrupt flag */ intel_idle_s2idle() local
1717 unsigned int eax, ebx, ecx, edx; sklh_idle_state_table_update() local
2057 unsigned int eax, ebx, ecx; intel_idle_init() local
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/openbmc/qemu/hw/arm/
H A Dhighbank.c4 * Copyright (c) 2010-2012 Calxeda
31 #include "qemu/error-report.h"
33 #include "hw/ide/ahci-sysbus.h"
39 #include "target/arm/cpu-qom.h"
100 #define TYPE_HIGHBANK_REGISTERS "highbank-regs"
113 .name = "highbank-regs",
126 s->regs[0x40] = 0x05F20121; in highbank_regs_reset()
127 s->regs[0x41] = 0x2; in highbank_regs_reset()
128 s->regs[0x42] = 0x05F30121; in highbank_regs_reset()
129 s->regs[0x43] = 0x05F40121; in highbank_regs_reset()
[all …]
/openbmc/u-boot/drivers/timer/
H A Dtsc_timer.c1 // SPDX-License-Identifier: GPL-2.0+
18 #include <asm/u-boot-x86.h>
40 if (gd->arch.x86_vendor != X86_VENDOR_INTEL) in native_calibrate_tsc()
51 crystal_freq = tsc_info.ecx / 1000; in native_calibrate_tsc()
54 switch (gd->arch.x86_model) { in native_calibrate_tsc()
72 return (crystal_freq * tsc_info.ebx / tsc_info.eax) / 1000; in native_calibrate_tsc()
77 if (gd->arch.x86_vendor != X86_VENDOR_INTEL) in cpu_mhz_from_cpuid()
87 * According to Intel 64 and IA-32 System Programming Guide,
107 /* TNG - Intel Atom processor Z3400 series */
109 /* VLV2 - Intel Atom processor E3000, Z3600, Z3700 series */
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Duvesafb.c1 // SPDX-License-Identifier: GPL-2.0-only
80 if (msg->seq >= UVESAFB_TASKS_MAX) in uvesafb_cn_callback()
84 task = uvfb_tasks[msg->seq]; in uvesafb_cn_callback()
86 if (!task || msg->ack != task->ack) { in uvesafb_cn_callback()
91 utask = (struct uvesafb_task *)msg->data; in uvesafb_cn_callback()
94 if (task->t.buf_len < utask->buf_len || in uvesafb_cn_callback()
95 utask->buf_len > msg->len - sizeof(*utask)) { in uvesafb_cn_callback()
100 uvfb_tasks[msg->seq] = NULL; in uvesafb_cn_callback()
103 memcpy(&task->t, utask, sizeof(*utask)); in uvesafb_cn_callback()
105 if (task->t.buf_len && task->buf) in uvesafb_cn_callback()
[all …]
H A Dvesafb.c1 // SPDX-License-Identifier: GPL-2.0-only
8 * (c) 1998 Gerd Knorr <kraxel@goldbach.in-berlin.de>
31 /* --------------------------------------------------------------------- */
43 .height = -1,
44 .width = -1,
68 /* --------------------------------------------------------------------- */
76 offset = (var->yoffset * info->fix.line_length + var->xoffset) / 4; in vesafb_pan_display()
83 "c" (offset), /* ECX */ in vesafb_pan_display()
93 int shift = 16 - depth; in vesa_setpalette()
94 int err = -EINVAL; in vesa_setpalette()
[all …]
/openbmc/linux/tools/power/x86/turbostat/
H A Dturbostat.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * turbostat -- show CPU frequency and C-state residency
44 * 1. built-in only, the sysfs counters are not here -- we learn of those at run-time
46 * matching on them for --show and --hide.
51 * Usually truncated to 7 characters, but also handles 18 columns for raw 64-bit counters
318 /* Indicates cores energy collection is per-core,
319 * not per-package. */
327 /* MSRs that are not yet in the kernel-provided header. */
369 unsigned long long mc6_us; /* duplicate as per-core for now, even though per module */
443 /* get_msr_sum() = sum + (get_msr() - last) */
[all …]
/openbmc/linux/arch/x86/kernel/
H A Dtsc.c1 // SPDX-License-Identifier: GPL-2.0-only
29 #include <asm/intel-family.h>
39 #define KHZ 1000
80 data->cyc2ns_offset = this_cpu_read(cyc2ns.data[idx].cyc2ns_offset); in __cyc2ns_read()
81 data->cyc2ns_mul = this_cpu_read(cyc2ns.data[idx].cyc2ns_mul); in __cyc2ns_read()
82 data->cyc2ns_shift = this_cpu_read(cyc2ns.data[idx].cyc2ns_shift); in __cyc2ns_read()
113 * cyc2ns_scale needs to be a 32-bit value so that 32-bit multiplication
114 * (64-bit result) can be used.
119 * -johnstul@us.ibm.com "math is hard, lets go shopping!"
163 * conversion algorithm shifting a 32-bit value (now specifies a 64-bit in __set_cyc2ns_scale()
[all …]
H A Dhpet.c1 // SPDX-License-Identifier: GPL-2.0-only
133 * is_hpet_enabled - Check whether the legacy HPET timer interrupt is enabled
210 hd.hd_irq[i] = hc->irq; in hpet_reserve_platform_timers()
212 switch (hc->mode) { in hpet_reserve_platform_timers()
215 hc->mode = HPET_MODE_DEVICE; in hpet_reserve_platform_timers()
219 hpet_reserve_timer(&hd, hc->num); in hpet_reserve_platform_timers()
235 if (hc->mode == HPET_MODE_UNUSED) { in hpet_select_device_channel()
236 hc->mode = HPET_MODE_DEVICE; in hpet_select_device_channel()
299 unsigned int channel = clockevent_to_channel(evt)->num; in hpet_clkevt_set_state_periodic()
304 delta = ((uint64_t)(NSEC_PER_SEC / HZ)) * evt->mult; in hpet_clkevt_set_state_periodic()
[all …]
/openbmc/qemu/target/i386/kvm/
H A Dkvm.c4 * Copyright (C) 2006-2008 Qumranet Technologies
11 * See the COPYING file in the top-level directory.
16 #include "qapi/qapi-events-run-state.h"
28 #include "standard-headers/asm-x86/kvm_para.h"
29 #include "hw/xen/interface/arch-x86/cpuid.h"
32 #include "host-cpu.h"
39 #include "../confidential-guest.h"
41 #include "xen-emu.h"
43 #include "hyperv-proto.h"
46 #include "qemu/host-utils.h"
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