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/openbmc/qemu/tests/qtest/
H A Dxlnx-can-test.c129 * This test will be transferring data from CAN0 and CAN1 through canbus. CAN0
130 * initiate the data transfer to can-bus, CAN1 receives the data. Test compares
131 * the data sent from CAN0 with received on CAN1.
146 /* Configure the CAN0 and CAN1. */ in test_can_bus()
152 /* Check here if CAN0 and CAN1 are in normal mode. */ in test_can_bus()
168 * This test is performing loopback mode on CAN0 and CAN1. Data sent from TX of
169 * each CAN0 and CAN1 are compared with RX register data for respective CAN.
197 /* Configure the CAN1 in loopback mode. */ in test_can_loopback()
202 /* Check here if CAN1 is set in loopback mode. */ in test_can_loopback()
215 * Enable filters for CAN1. This will filter incoming messages with ID. In this
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/openbmc/linux/drivers/net/can/sja1000/
H A Dtscan1.c3 * tscan1.c: driver for Technologic Systems TS-CAN1 PC104 boards
9 * - Getting started with TS-CAN1, Technologic Systems, Feb 2022
10 * https://docs.embeddedts.com/TS-CAN1
21 MODULE_DESCRIPTION("Driver for Technologic Systems TS-CAN1 PC104 boards");
77 /* Probe for a TS-CAN1 board with JP2:JP1 jumper setting ID */
144 netdev_info(netdev, "TS-CAN1 at 0x%lx 0x%lx irq %d\n", in tscan1_probe()
/openbmc/linux/Documentation/devicetree/bindings/net/can/
H A Dst,stm32-bxcan.yaml69 SRAM memory shared by the two bxCAN cells (CAN1 primary and CAN2
87 can1: can@40006400 {
92 resets = <&rcc STM32F4_APB1_RESET(CAN1)>;
93 clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>;
H A Drenesas,rcar-canfd.yaml125 - description: CAN1 error interrupt
126 - description: CAN1 transmit interrupt
127 - description: CAN1 transmit/receive FIFO receive completion interrupt
/openbmc/linux/arch/arm64/boot/dts/renesas/
H A Dcat875.dtsi40 &can1 {
63 can1_pins: can1 {
65 function = "can1";
H A Dhihope-rzg2-ex.dtsi42 &can1 {
79 can1_pins: can1 {
81 function = "can1";
H A Drzg2lc-smarc-pinfunction.dtsi17 can1_pins: can1 {
25 can1-stb-hog {
32 can1_pins: can1 {
H A Dr9a07g044c2-smarc.dts14 * SW1-3 : SW_SCIF_CAN (1: CAN1; 0: SCIF1)
15 * SW1-4 : SW_RSPI_CAN (1: CAN1; 0: RSPI1)
H A Drzg2ul-smarc-pinfunction.dtsi29 can1_pins: can1 {
35 can1-stb-hog {
/openbmc/linux/arch/arm/boot/dts/renesas/
H A Diwg20d-q7-dbcm-ca.dtsi32 &can1 {
98 can1_pins: can1 {
100 function = "can1";
H A Dr8a7745-iwg22d-sodimm-dbhd-ca.dts54 &can1 {
116 can1_pins: can1 {
118 function = "can1";
H A Dr9a06g032-rzn1d400-db.dts33 /* Assuming CN10/CN11 are wired for CAN1 */
37 &can1 {
41 /* Please only enable can0 or can1, depending on CN10/CN11 */
H A Dr8a7792-wheat.dts142 can1_pins: can1 {
144 function = "can1";
187 &can1 {
/openbmc/u-boot/arch/arm/dts/
H A Dzynqmp-zc1751-xm018-dc4.dts21 can1 = &can1;
50 &can1 {
H A Dat91sam9x5_can.dtsi41 can1: can@f8004000 { label
61 can1 {
H A Dsama5d3_can.dtsi25 can1 {
62 can1: can@f8010000 { label
H A Dzynqmp-zc1751-xm016-dc2.dts21 can1 = &can1;
48 &can1 {
/openbmc/linux/arch/arm/boot/dts/nxp/imx/
H A Dimx6qdl-skov-cpu.dtsi14 can0 = &can1;
15 can1 = &can2;
133 reg_can1_stby: regulator-can1-stby {
137 regulator-name = "can1-3v3";
194 &can1 {
/openbmc/linux/Documentation/devicetree/bindings/reset/
H A Dzynq-reset.txt46 257: can1 reset
48 259: can1 ref reset
/openbmc/linux/arch/arm/boot/dts/microchip/
H A Dat91sam9x5_can.dtsi26 can1: can@f8004000 { label
46 can1 {
H A Dsama5d3_can.dtsi24 can1 {
45 can1: can@f8010000 { label
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dloongson,ls2k-pinctrl.yaml42 enum: [gpio, sdio, can1, can0, pwm3, pwm2, pwm1, pwm0, i2c1, i2c0,
47 enum: [gpio, sdio, can1, can0, pwm3, pwm2, pwm1, pwm0, i2c1, i2c0,
/openbmc/linux/arch/powerpc/boot/dts/fsl/
H A Dp1010si-pre.dtsi54 can1 = &can1;
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Dzynq-7000.txt61 20: can1
99 "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
/openbmc/linux/drivers/pinctrl/
H A Dpinctrl-loongson2.c110 PMX_GROUP(can1, 0x0, 17),
125 SPECIFIC_GROUP(can1);
140 "can1", "can0",
152 FUNCTION(can1),

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