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/openbmc/u-boot/drivers/gpio/
H A Dda8xx_gpio.c1 // SPDX-License-Identifier: GPL-2.0+
14 #include <dt-bindings/gpio/gpio.h>
28 #define pinmux(x) (&davinci_syscfg_regs->pinmux[x])
32 { pinmux(13), 8, 6 }, /* GP0[0] */
33 { pinmux(13), 8, 7 },
34 { pinmux(14), 8, 0 },
35 { pinmux(14), 8, 1 },
36 { pinmux(14), 8, 2 },
37 { pinmux(14), 8, 3 },
38 { pinmux(14), 8, 4 },
[all …]
/openbmc/linux/lib/
H A Dclz_tab.c1 // SPDX-License-Identifier: GPL-2.0
11 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
12 8, 8, 8, 8, 8, 8, 8, 8,
13 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
14 8, 8, 8, 8, 8, 8, 8, 8,
15 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
16 8, 8, 8, 8, 8, 8, 8, 8,
17 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
18 8, 8, 8, 8, 8, 8, 8, 8,
/openbmc/u-boot/include/fsl-mc/
H A Dfsl_dprc.h1 /* SPDX-License-Identifier: GPL-2.0+ */
5 * Copyright 2013-2016 Freescale Semiconductor, Inc.
48 MC_CMD_OP(cmd, 0, 32, 16, uint16_t, cfg->icid); \
49 MC_CMD_OP(cmd, 0, 0, 32, uint32_t, cfg->options); \
50 MC_CMD_OP(cmd, 1, 32, 32, int, cfg->portal_id); \
51 MC_CMD_OP(cmd, 2, 0, 8, char, cfg->label[0]);\
52 MC_CMD_OP(cmd, 2, 8, 8, char, cfg->label[1]);\
53 MC_CMD_OP(cmd, 2, 16, 8, char, cfg->label[2]);\
54 MC_CMD_OP(cmd, 2, 24, 8, char, cfg->label[3]);\
55 MC_CMD_OP(cmd, 2, 32, 8, char, cfg->label[4]);\
[all …]
/openbmc/u-boot/drivers/mtd/nand/raw/
H A Dnand_ids.c28 LEGACY_ID_NAND("NAND 1MiB 5V 8-bit", 0x6e, 1, SZ_4K, SP_OPTIONS),
29 LEGACY_ID_NAND("NAND 2MiB 5V 8-bit", 0x64, 2, SZ_4K, SP_OPTIONS),
30 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS),
31 LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS),
32 LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS),
33 LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS),
35 LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xe6, 8, SZ_8K, SP_OPTIONS),
42 {"TC58NVG0S3E 1G 3.3V 8-bit",
44 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512),
46 {"TC58NVG2S0F 4G 3.3V 8-bit",
[all …]
/openbmc/linux/include/dt-bindings/iio/
H A Dqcom,spmi-adc7-pm8350b.h1 /* SPDX-License-Identifier: GPL-2.0-only */
13 #include <dt-bindings/iio/qcom,spmi-vadc.h>
16 #define PM8350B_ADC7_REF_GND (PM8350B_SID << 8 | ADC7_REF_GND)
17 #define PM8350B_ADC7_1P25VREF (PM8350B_SID << 8 | ADC7_1P25VREF)
18 #define PM8350B_ADC7_VREF_VADC (PM8350B_SID << 8 | ADC7_VREF_VADC)
19 #define PM8350B_ADC7_DIE_TEMP (PM8350B_SID << 8 | ADC7_DIE_TEMP)
21 #define PM8350B_ADC7_AMUX_THM1 (PM8350B_SID << 8 | ADC7_AMUX_THM1)
22 #define PM8350B_ADC7_AMUX_THM2 (PM8350B_SID << 8 | ADC7_AMUX_THM2)
23 #define PM8350B_ADC7_AMUX_THM3 (PM8350B_SID << 8 | ADC7_AMUX_THM3)
24 #define PM8350B_ADC7_AMUX_THM4 (PM8350B_SID << 8 | ADC7_AMUX_THM4)
[all …]
H A Dqcom,spmi-adc7-pm8350.h1 /* SPDX-License-Identifier: GPL-2.0-only */
9 #include <dt-bindings/iio/qcom,spmi-vadc.h>
12 #define PM8350_ADC7_REF_GND(sid) ((sid) << 8 | ADC7_REF_GND)
13 #define PM8350_ADC7_1P25VREF(sid) ((sid) << 8 | ADC7_1P25VREF)
14 #define PM8350_ADC7_VREF_VADC(sid) ((sid) << 8 | ADC7_VREF_VADC)
15 #define PM8350_ADC7_DIE_TEMP(sid) ((sid) << 8 | ADC7_DIE_TEMP)
17 #define PM8350_ADC7_AMUX_THM1(sid) ((sid) << 8 | ADC7_AMUX_THM1)
18 #define PM8350_ADC7_AMUX_THM2(sid) ((sid) << 8 | ADC7_AMUX_THM2)
19 #define PM8350_ADC7_AMUX_THM3(sid) ((sid) << 8 | ADC7_AMUX_THM3)
20 #define PM8350_ADC7_AMUX_THM4(sid) ((sid) << 8 | ADC7_AMUX_THM4)
[all …]
/openbmc/linux/drivers/mtd/nand/raw/
H A Dnand_ids.c1 // SPDX-License-Identifier: GPL-2.0-only
29 {"TC58NVG0S3E 1G 3.3V 8-bit",
31 SZ_2K, SZ_128, SZ_128K, 0, 8, 64, NAND_ECC_INFO(1, SZ_512), },
32 {"TC58NVG2S0F 4G 3.3V 8-bit",
34 SZ_4K, SZ_512, SZ_256K, 0, 8, 224, NAND_ECC_INFO(4, SZ_512) },
35 {"TC58NVG2S0H 4G 3.3V 8-bit",
37 SZ_4K, SZ_512, SZ_256K, 0, 8, 256, NAND_ECC_INFO(8, SZ_512) },
38 {"TC58NVG3S0F 8G 3.3V 8-bit",
40 SZ_4K, SZ_1K, SZ_256K, 0, 8, 232, NAND_ECC_INFO(4, SZ_512) },
41 {"TC58NVG5D2 32G 3.3V 8-bit",
[all …]
/openbmc/linux/arch/powerpc/kernel/
H A Didle_book3s.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
10 * The platform / CPU caller must ensure SPRs and any other non-GPR
15 #include <asm/asm-offsets.h>
16 #include <asm/ppc-opcode.h>
60 std r2,-8*1(r1)
61 std r14,-8*2(r1)
62 std r15,-8*3(r1)
63 std r16,-8*4(r1)
64 std r17,-8*5(r1)
65 std r18,-8*6(r1)
[all …]
/openbmc/linux/drivers/mfd/
H A Dmt6370.c1 // SPDX-License-Identifier: GPL-2.0-only
38 REGMAP_IRQ_REG_LINE(MT6370_IRQ_DIRCHGON, 8),
39 REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_TREG, 8),
40 REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_AICR, 8),
41 REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_MIVR, 8),
42 REGMAP_IRQ_REG_LINE(MT6370_IRQ_PWR_RDY, 8),
43 REGMAP_IRQ_REG_LINE(MT6370_IRQ_FL_CHG_VINOVP, 8),
44 REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_VSYSUV, 8),
45 REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_VSYSOV, 8),
46 REGMAP_IRQ_REG_LINE(MT6370_IRQ_CHG_VBATOV, 8),
[all …]
/openbmc/linux/arch/powerpc/boot/
H A Dwii-head.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * arch/powerpc/boot/wii-head.S
6 * Copyright (C) 2008-2009 The GameCube Linux Team
14 * - if the data and instruction caches are enabled or not
15 * - if the MMU is enabled or not
16 * - if the high BATs are enabled or not
32 mflr 8
33 clrlwi 8, 8, 3 /* convert to a real address */
34 addi 8, 8, _mmu_off - 1b
35 mtsrr0 8
[all …]
H A Dgamecube-head.S1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * arch/powerpc/boot/gamecube-head.S
6 * Copyright (C) 2004-2009 The GameCube Linux Team
14 * - if the data and instruction caches are enabled or not
15 * - if the MMU is enabled or not
31 mflr 8
32 clrlwi 8, 8, 3 /* convert to a real address */
33 addi 8, 8, _mmu_off - 1b
34 mtsrr0 8
42 li 8, 0
[all …]
/openbmc/qemu/linux-user/loongarch64/
H A Dvdso.S6 * SPDX-License-Identifier: GPL-2.0-or-later
11 #include "vdso-asmoffset.h"
19 .size \name, . - \name
58 .cfi_offset 1, B_GR + 1 * 8
59 .cfi_offset 2, B_GR + 2 * 8
60 .cfi_offset 3, B_GR + 3 * 8
61 .cfi_offset 4, B_GR + 4 * 8
62 .cfi_offset 5, B_GR + 5 * 8
63 .cfi_offset 6, B_GR + 6 * 8
64 .cfi_offset 7, B_GR + 7 * 8
[all …]
/openbmc/u-boot/arch/nios2/lib/
H A Dlibgcc.c1 // SPDX-License-Identifier: GPL-2.0+
32 #define BITS_PER_UNIT 8
43 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
44 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
45 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
46 8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8
57 const word_type bm = (sizeof (Wtype) * BITS_PER_UNIT) - b; in __ashldi3()
63 w.s.high = (UWtype) uu.s.low << -bm; in __ashldi3()
83 const word_type bm = (sizeof (Wtype) * BITS_PER_UNIT) - b; in __ashrdi3()
89 w.s.high = uu.s.high >> (sizeof (Wtype) * BITS_PER_UNIT - 1); in __ashrdi3()
[all …]
/openbmc/u-boot/drivers/pinctrl/uniphier/
H A Dpinctrl-uniphier-pxs2.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2015-2016 Socionext Inc.
11 #include "pinctrl-uniphier.h"
20 static const int ether_mii_muxvals[] = {8, 8, 8, 8, 10, 10, 10, 10, 10, 10, 10,
25 static const int ether_rgmii_muxvals[] = {8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
26 8, 8, 8, 8};
29 static const int ether_rmii_muxvals[] = {8, 8, 8, 8, 9, 9, 9, 9, 9, 9, 9, 9};
31 static const int i2c0_muxvals[] = {8, 8};
33 static const int i2c1_muxvals[] = {8, 8};
35 static const int i2c2_muxvals[] = {8, 8};
[all …]
/openbmc/linux/Documentation/devicetree/bindings/ptp/
H A Dptp-idtcm.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/ptp/ptp-idtcm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Vincent Cheng <vincent.cheng.xh@renesas.com>
16 - idt,8a34000
17 - idt,8a34001
18 - idt,8a34002
19 - idt,8a34003
20 - idt,8a34004
[all …]
/openbmc/linux/arch/arm64/crypto/
H A Dsha3-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sha3-ce-core.S - core SHA-3 transform using v8.2 Crypto Extensions
15 .irp b,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
46 ld1 { v0.1d- v3.1d}, [x0]
47 ld1 { v4.1d- v7.1d}, [x8], #32
48 ld1 { v8.1d-v11.1d}, [x8], #32
49 ld1 {v12.1d-v15.1d}, [x8], #32
50 ld1 {v16.1d-v19.1d}, [x8], #32
51 ld1 {v20.1d-v23.1d}, [x8], #32
59 ld1 {v25.8b-v28.8b}, [x1], #32
[all …]
/openbmc/linux/Documentation/driver-api/media/drivers/ccs/
H A Dccs-regs.asc1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
2 # Copyright (C) 2019--2020 Intel Corporation
5 # - f field LSB MSB rflags
6 # - e enum value # after a field
7 # - e enum value [LSB MSB]
8 # - b bool bit
9 # - l arg name min max elsize [discontig...]
12 # 8, 16, 32 register bits (default is 8)
20 module_revision_number_major 0x0002 8
21 frame_count 0x0005 8
[all …]
/openbmc/qemu/linux-user/hppa/
H A Dvdso.S6 * SPDX-License-Identifier: GPL-2.0-or-later
10 #include "vdso-asmoffset.h"
18 * a 64-byte boundary by 0, 4 or 5 instructions. Since the vdso trampoline
28 /* arch/parisc/kernel/asm-offsets.c */
30 (offsetof_sigcontext - PARISC_RT_SIGFRAME_SIZE32)
54 .cfi_def_cfa 30, -PARISC_RT_SIGFRAME_SIZE32 + offsetof_sigcontext
64 .cfi_offset 8, offsetof_sigcontext_gr + 8 * 4
90 .cfi_offset 32, offsetof_sigcontext_fr + 4 * 8
91 .cfi_offset 33, offsetof_sigcontext_fr + 4 * 8 + 4
92 .cfi_offset 34, offsetof_sigcontext_fr + 5 * 8
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-benchmark/lmbench/lmbench/
H A D0001-doc-Fix-typos-in-manual-pages.patch6 Signed-off-by: He Zhe <zhe.he@windriver.com>
7 ---
8 Upstream-Status: Pending
10 doc/bw_mem.8 | 2 +-
11 doc/lat_fcntl.8 | 2 +-
12 doc/lat_fifo.8 | 2 +-
13 doc/lat_http.8 | 6 +++---
14 doc/lat_select.8 | 2 +-
15 doc/lat_sig.8 | 2 +-
16 6 files changed, 8 insertions(+), 8 deletions(-)
[all …]
/openbmc/qemu/include/libdecnumber/
H A DdecDPD.h29 02110-1301, USA. */
31 /* ------------------------------------------------------------------------ */
33 /* [Automatically generated -- do not edit. 2007.05.05] */
34 /* ------------------------------------------------------------------------ */
35 /* ------------------------------------------------------------------------ */
41 /* uint16_t BCD2DPD[2458]; -- BCD -> DPD (0x999 => 2457) */
42 /* uint16_t BIN2DPD[1000]; -- Bin -> DPD (999 => 2457) */
43 /* uint8_t BIN2CHAR[4001]; -- Bin -> CHAR (999 => '\3' '9' '9' '9') */
44 /* uint8_t BIN2BCD8[4000]; -- Bin -> bytes (999 => 9 9 9 3) */
45 /* uint16_t DPD2BCD[1024]; -- DPD -> BCD (0x3FF => 0x999) */
[all …]
/openbmc/qemu/gdb-xml/
H A Davr-cpu.xml2 <!-- Copyright (C) 2018-2019 Free Software Foundation, Inc.
6 notice and this notice are preserved. -->
8 <!-- Register numbers are hard-coded in order to maintain backward
10 register descriptions. -->
12 <!DOCTYPE feature SYSTEM "gdb-target.dtd">
14 <reg name="r0" bitsize="8" type="int" regnum="0"/>
15 <reg name="r1" bitsize="8" type="int"/>
16 <reg name="r2" bitsize="8" type="int"/>
17 <reg name="r3" bitsize="8" type="int"/>
18 <reg name="r4" bitsize="8" type="int"/>
[all …]
/openbmc/linux/drivers/gpu/drm/msm/disp/
H A Dmdp_format.c1 // SPDX-License-Identifier: GPL-2.0-only
89 FMT(ARGB8888, 8, 8, 8, 8, 1, 0, 2, 3, true, true, 4, 4,
91 FMT(ABGR8888, 8, 8, 8, 8, 2, 0, 1, 3, true, true, 4, 4,
93 FMT(RGBA8888, 8, 8, 8, 8, 3, 1, 0, 2, true, true, 4, 4,
95 FMT(BGRA8888, 8, 8, 8, 8, 3, 2, 0, 1, true, true, 4, 4,
97 FMT(XRGB8888, 8, 8, 8, 8, 1, 0, 2, 3, false, true, 4, 4,
99 FMT(XBGR8888, 8, 8, 8, 8, 2, 0, 1, 3, false, true, 4, 4,
101 FMT(RGBX8888, 8, 8, 8, 8, 3, 1, 0, 2, false, true, 4, 4,
103 FMT(BGRX8888, 8, 8, 8, 8, 3, 2, 0, 1, false, true, 4, 4,
105 FMT(RGB888, 0, 8, 8, 8, 1, 0, 2, 0, false, true, 3, 3,
[all …]
/openbmc/linux/arch/powerpc/perf/
H A Dhv-gpci-requests.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 #include "req-gen/_begin.h"
22 * - starting_index_kind is one of the following, depending on the event:
24 * hw_chip_id: hardware chip id or -1 for current hw chip
28 * 0xffffffffffffffff: or -1, which means it is irrelavant for the event
43 * - expose secondary index (if any counter ever uses it, only 0xA0
45 * - embed versioning info
46 * - include counter descriptions
52 REQUEST(__count(0, 8, processor_time_in_timebase_cycles)
73 REQUEST(__field(0, 8, partition_id)
[all …]
/openbmc/linux/arch/arm/crypto/
H A Daes-ce-core.S1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * aes-ce-core.S - AES in CBC/CTR/XTS mode using ARMv8 Crypto Extensions
12 .arch armv8-a
13 .fpu crypto-neon-fp-armv8
17 aese.8 \state, \key
18 aesmc.8 \state, \state
22 aesd.8 \state, \key
23 aesimc.8 \state, \state
38 aese.8 q0, \key2
44 aesd.8 q0, \key2
[all …]
/openbmc/linux/Documentation/gpu/
H A Dafbc.rst1 .. SPDX-License-Identifier: GPL-2.0+
8 It provides fine-grained random access and minimizes the amount of
21 AFBC streams can contain several components - where a component
37 reside in the least-significant bits of the corresponding linear
42 * Component 0: R(8)
43 * Component 1: G(8)
44 * Component 2: B(8)
45 * Component 3: A(8)
49 * Component 0: R(8)
50 * Component 1: G(8)
[all …]

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