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/openbmc/linux/arch/m68k/include/uapi/asm/
H A Dbootinfo-hp300.h25 #define HP_320 0 /* 16MHz 68020+HP MMU+16K external cache */
26 #define HP_330 1 /* 16MHz 68020+68851 MMU */
27 #define HP_340 2 /* 16MHz 68030 */
28 #define HP_345 3 /* 50MHz 68030+32K external cache */
29 #define HP_350 4 /* 25MHz 68020+HP MMU+32K external cache */
30 #define HP_360 5 /* 25MHz 68030 */
31 #define HP_370 6 /* 33MHz 68030+64K external cache */
32 #define HP_375 7 /* 50MHz 68030+32K external cache */
33 #define HP_380 8 /* 25MHz 68040 */
34 #define HP_385 9 /* 33MHz 68040 */
[all …]
/openbmc/linux/Documentation/devicetree/bindings/clock/
H A Darmada3700-periph-clock.txt36 0 gbe-50 50 MHz parent clock for Gigabit Ethernet
38 2 gbe-125 125 MHz parent clock for Gigabit Ethernet
39 3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
40 4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
41 5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
42 6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
H A Dstarfive,jh7100-clkgen.yaml22 - description: Main clock source (25 MHz)
23 - description: Application-specific clock source (12-27 MHz)
24 - description: RMII reference clock (50 MHz)
25 - description: RGMII RX clock (125 MHz)
/openbmc/linux/Documentation/scsi/
H A Daic7xxx.rst26 aic7770 10 EISA/VL 10MHz 16Bit 4 1
27 aic7850 10 PCI/32 10MHz 8Bit 3
28 aic7855 10 PCI/32 10MHz 8Bit 3
29 aic7856 10 PCI/32 10MHz 8Bit 3
30 aic7859 10 PCI/32 20MHz 8Bit 3
31 aic7860 10 PCI/32 20MHz 8Bit 3
32 aic7870 10 PCI/32 10MHz 16Bit 16
33 aic7880 10 PCI/32 20MHz 16Bit 16
34 aic7890 20 PCI/32 40MHz 16Bit 16 3 4 5 6 7 8
35 aic7891 20 PCI/64 40MHz 16Bit 16 3 4 5 6 7 8
[all …]
/openbmc/u-boot/doc/
H A DREADME.m54418twr119 make M54418TWR_config, or - default to spi serial flash boot, 50Mhz input clock
120 make M54418TWR_nand_mii_config, or - default to nand flash boot, mii mode, 25Mhz input clock
121 make M54418TWR_nand_rmii_config, or - default to nand flash boot, rmii mode, 50Mhz input clock
122 …make M54418TWR_nand_rmii_lowfreq_config, or - default to nand flash boot, rmii mode, 50Mhz input c…
123 make M54418TWR_serial_mii_config, or - default to spi serial flash boot, 25Mhz input clock
124 make M54418TWR_serial_rmii_config, or - default to spi serial flash boot, 50Mhz input clock
135 CPU CLK 250 MHz BUS CLK 125 MHz FLB CLK 125 MHz
136 INP CLK 50 MHz VCO CLK 500 MHz
182 cpufreq = 250 MHz
183 busfreq = 125 MHz
[all …]
/openbmc/linux/drivers/phy/intel/
H A Dphy-intel-keembay-emmc.c59 unsigned int mhz; in keembay_emmc_phy_power() local
84 mhz = DIV_ROUND_CLOSEST(clk_get_rate(priv->emmcclk), 1000000); in keembay_emmc_phy_power()
85 if (mhz <= 200 && mhz >= 170) in keembay_emmc_phy_power()
87 else if (mhz <= 170 && mhz >= 140) in keembay_emmc_phy_power()
89 else if (mhz <= 140 && mhz >= 110) in keembay_emmc_phy_power()
91 else if (mhz <= 110 && mhz >= 80) in keembay_emmc_phy_power()
93 else if (mhz <= 80 && mhz >= 50) in keembay_emmc_phy_power()
99 if (mhz > 175) in keembay_emmc_phy_power()
100 dev_warn(&phy->dev, "Unsupported rate: %d MHz\n", mhz); in keembay_emmc_phy_power()
125 0, 50); in keembay_emmc_phy_power()
[all …]
/openbmc/u-boot/arch/arm/mach-omap2/am33xx/
H A Dclock_am33xx.c67 { /* 19.2 MHz */
68 {125, 3, 2, -1, -1, -1, -1}, /* OPP 50 */
75 { /* 24 MHz */
76 {25, 0, 2, -1, -1, -1, -1}, /* OPP 50 */
83 { /* 25 MHz */
84 {24, 0, 2, -1, -1, -1, -1}, /* OPP 50 */
91 { /* 26 MHz */
92 {300, 12, 2, -1, -1, -1, -1}, /* OPP 50 */
102 {625, 11, -1, -1, 10, 8, 4}, /* 19.2 MHz */
103 {125, 2, -1, -1, 10, 8, 4}, /* 24 MHz */
[all …]
/openbmc/linux/arch/arm/mach-omap2/
H A Dopp2xxx.h123 /* 2420-PRCM III 532MHz core */
124 #define RIII_CLKSEL_L3 (4 << 0) /* 133MHz */
125 #define RIII_CLKSEL_L4 (2 << 5) /* 66.5MHz */
126 #define RIII_CLKSEL_USB (4 << 25) /* 33.25MHz */
131 #define RIII_CLKSEL_MPU (2 << 0) /* 266MHz */
133 #define RIII_CLKSEL_DSP (3 << 0) /* c5x - 177.3MHz */
134 #define RIII_CLKSEL_DSP_IF (2 << 5) /* c5x - 88.67MHz */
136 #define RIII_CLKSEL_IVA (6 << 8) /* iva1 - 88.67MHz */
141 #define RIII_CLKSEL_GFX (2 << 0) /* 66.5MHz */
144 /* 2420-PRCM II 600MHz core */
[all …]
/openbmc/linux/drivers/clk/uniphier/
H A Dclk-uniphier-sys.c28 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 32), \
29 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
32 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 48), \
33 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x2104, 2)
36 UNIPHIER_CLK_FACTOR("nand-50m", -1, "spll", 1, 40), \
37 UNIPHIER_CLK_GATE("nand", (idx), "nand-50m", 0x210c, 0)
87 UNIPHIER_CLK_FACTOR("spll", -1, "ref", 65, 1), /* 1597.44 MHz */
88 UNIPHIER_CLK_FACTOR("upll", -1, "ref", 6000, 512), /* 288 MHz */
89 UNIPHIER_CLK_FACTOR("a2pll", -1, "ref", 24, 1), /* 589.824 MHz */
90 UNIPHIER_CLK_FACTOR("vpll27a", -1, "ref", 5625, 512), /* 270 MHz */
[all …]
/openbmc/linux/Documentation/fb/
H A Dviafb.modes10 # 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock)
29 # D: 25.175 MHz, H: 31.469 kHz, V: 59.94 Hz
32 # D: 24.823 MHz, H: 39.780 kHz, V: 60.00 Hz
35 # 640x480, 75 Hz, Non-Interlaced (31.50 MHz dotclock)
53 # D: 31.50 MHz, H: 37.500 kHz, V: 75.00 Hz
56 # 640x480, 85 Hz, Non-Interlaced (36.000 MHz dotclock)
74 # D: 36.000 MHz, H: 43.269 kHz, V: 85.00 Hz
77 # 640x480, 100 Hz, Non-Interlaced (43.163 MHz dotclock)
95 # D: 43.163 MHz, H: 50.900 kHz, V: 100.00 Hz
98 # 640x480, 120 Hz, Non-Interlaced (52.406 MHz dotclock)
[all …]
/openbmc/linux/drivers/net/wireless/intel/iwlwifi/mvm/
H A Drfi.c11 * DDR needs frequency in units of 16.666MHz, so provide FW with the
15 /* frequency 2667MHz */
16 {cpu_to_le16(160), {50, 58, 60, 62, 64, 52, 54, 56},
20 /* frequency 2933MHz */
27 /* frequency 3200MHz */
32 /* frequency 3733MHz */
37 /* frequency 4000MHz */
42 /* frequency 4267MHz */
47 /* frequency 4400MHz */
52 /* frequency 5200MHz */
[all …]
/openbmc/u-boot/board/freescale/s32v234evb/
H A Dclock.c15 * refclk_freq - input referece clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ)
69 * refclk_freq - input reference clock frequency (FXOSC - 40 MHZ, FIRC - 48 MHZ)
191 /* setup the sys clock divider for CORE_CLK (1000MHz) */ in setup_sys_clocks()
195 /* setup the sys clock divider for CORE2_CLK (500MHz) */ in setup_sys_clocks()
198 /* setup the sys clock divider for SYS3_CLK (266 MHz) */ in setup_sys_clocks()
202 /* setup the sys clock divider for SYS6_CLK (133 Mhz) */ in setup_sys_clocks()
214 * (source: PERIPH_PLL_PHI_0/5, PERI_CLK - 80 MHz) in setup_aux_clocks()
219 /* setup the aux clock divider for LIN_CLK (40MHz) */ in setup_aux_clocks()
223 /* setup the aux clock divider for ENET_TIME_CLK (50MHz) */ in setup_aux_clocks()
227 /* setup the aux clock divider for ENET_CLK (50MHz) */ in setup_aux_clocks()
[all …]
/openbmc/linux/drivers/ata/
H A Dpata_ftide010.c79 /* 0 = 50 MHz, 1 = 66 MHz */
94 * reference clock which is 30 nanoseconds per unit at 66MHz and 20
95 * nanoseconds per unit at 50 MHz. The PIO timings assume 33MHz speed for
103 * word DMA, Mode 0, 1, and 2 at 50 MHz. Range 0..15.
105 * multi word DMA, Mode 0, 1 and 2 at 50 MHz. Range 0..15.
107 * word DMA, Mode 0, 1 and 2 at 66 MHz. Range 0..15.
109 * multi word DMA, Mode 0, 1 and 2 at 66 MHz. Range 0..15.
111 * DMA, Mode 0, 1, 2, 3, 4 and 5 at 50 MHz. Range 0..7.
113 * multi word DMA, Mode 0, 1, 2, 3, 4 and 5 at 50 MHz, Range 0..7.
115 * word DMA, Mode 0, 1, 2, 3, 4, 5 and 6 at 66 MHz. Range 0..7.
[all …]
H A Dpata_hpt37x.c595 * @freq: Reported frequency in MHz
597 * Turn the timing data into a clock slot (0 for 33, 1 for 40, 2 for 50
598 * and 3 for 66Mhz)
604 return 0; /* 33Mhz slot */ in hpt37x_clock_slot()
606 return 1; /* 40Mhz slot */ in hpt37x_clock_slot()
608 return 2; /* 50Mhz slot */ in hpt37x_clock_slot()
609 return 3; /* 60Mhz slot */ in hpt37x_clock_slot()
627 udelay(50); in hpt37x_calibrate_dpll()
688 freq = (fcnt * base) / 192; /* in MHz */ in hpt37x_pci_clock()
696 return 50; in hpt37x_pci_clock()
[all …]
/openbmc/u-boot/arch/arm/include/asm/arch-s32v234/
H A Dmc_cgm_regs.h178 /* ARM_PLL_PHI1_DFS1_FREQ - 266 Mhz */
182 /* ARM_PLL_PHI1_DFS2_REQ - 600 Mhz */
186 /* ARM_PLL_PHI1_DFS3_FREQ - 600 Mhz */
192 #define ARM_PLL_PLLDV_MFD (50)
204 /* ENET_PLL_PHI1_DFS1_FREQ - 350 Mhz*/
208 /* ENET_PLL_PHI1_DFS2_FREQ - 350 Mhz*/
212 /* ENET_PLL_PHI1_DFS3_FREQ - 320 Mhz*/
216 /* ENET_PLL_PHI1_DFS1_FREQ - 50 Mhz*/
222 #define ENET_PLL_PLLDV_MFD (50)
227 /* DDR_PLL_PHI1_DFS1_FREQ - 500 Mhz */
[all …]
/openbmc/u-boot/board/samsung/odroid/
H A Dodroid.c126 /* Set APLL to 1000MHz */ in board_clock_init()
149 * Set dividers for MOUTcore = 1000 MHz in board_clock_init()
150 * coreout = MOUT / (ratio + 1) = 1000 MHz (0) in board_clock_init()
151 * corem0 = armclk / (ratio + 1) = 333 MHz (2) in board_clock_init()
152 * corem1 = armclk / (ratio + 1) = 166 MHz (5) in board_clock_init()
153 * periph = armclk / (ratio + 1) = 1000 MHz (0) in board_clock_init()
154 * atbout = MOUT / (ratio + 1) = 200 MHz (4) in board_clock_init()
155 * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1) in board_clock_init()
156 * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0) in board_clock_init()
157 * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk) in board_clock_init()
[all …]
/openbmc/linux/drivers/video/fbdev/
H A Dmacmodes.c36 /* 512x384, 60Hz, Non-Interlaced (15.67 MHz dot clock) */
40 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
44 /* 640x480, 67Hz, Non-Interlaced (30.0 MHz dotclock) */
48 /* 640x870, 75Hz (portrait), Non-Interlaced (57.28 MHz dot clock) */
52 /* 800x600, 56 Hz, Non-Interlaced (36.00 MHz dotclock) */
56 /* 800x600, 60 Hz, Non-Interlaced (40.00 MHz dotclock) */
60 /* 800x600, 72 Hz, Non-Interlaced (50.00 MHz dotclock) */
64 /* 800x600, 75 Hz, Non-Interlaced (49.50 MHz dotclock) */
68 /* 832x624, 75Hz, Non-Interlaced (57.6 MHz dotclock) */
72 /* 1024x768, 60 Hz, Non-Interlaced (65.00 MHz dotclock) */
[all …]
/openbmc/linux/arch/arm/mach-pxa/
H A Dsleep.S62 @ set SDCLKx divide-by-2 bits (this is part of a workaround for Errata 50)
67 @ with core operating above 91 MHz
68 @ (see Errata 50, ...processor does not exit from sleep...)
104 @ about suspending with PXBus operating above 133MHz
124 orrne r7, r7, #1 @@ 99.53MHz
151 @ need 6 13-MHz cycles before changing PWRMODE
152 @ just set frequency to 91-MHz... 6*91/13 = 42
/openbmc/u-boot/board/k+p/kp_imx53/
H A Dkp_imx53.c112 /* Set VDDGP to 1.110V for 800 MHz on SW1 */ in power_init()
132 * CPU clock set to 800MHz and DDR to 400MHz in setup_clocks()
136 printf("CPU: Switch CPU clock to 800MHZ failed\n"); in setup_clocks()
141 printf("CPU: Switch DDR clock to 400MHz failed\n"); in setup_clocks()
175 udelay(50); in eth_phy_reset()
179 udelay(50); in eth_phy_reset()
/openbmc/linux/drivers/cpufreq/
H A Ds5pv210-cpufreq.c87 /* APLL M,P,S values for 1G/800Mhz */
91 /* Use 800MHz when entering sleep mode */
275 * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287 in s5pv210_target()
294 * SCLKA2M(200/1=200)->(200/4=50)Mhz in s5pv210_target()
308 * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX in s5pv210_target()
309 * (200/4=50)->(667/4=166)Mhz in s5pv210_target()
322 * 3. DMC1 refresh count for 133Mhz if (index == L4) is in s5pv210_target()
324 * code. 0x287@83Mhz in s5pv210_target()
375 /* 5. Set Lock time = 30us*24Mhz = 0x2cf */ in s5pv210_target()
393 * 7. Change source clock from SCLKMPLL(667Mhz) in s5pv210_target()
[all …]
/openbmc/u-boot/board/siemens/rut/
H A Dboard.c229 .hfp = 50, /* no spec, "don't care" values */
230 .hbp = 50,
231 .hsw = 50,
232 .vfp = 50,
233 .vbp = 50,
234 .vsw = 50,
235 .pxl_clk = 35910000, /* tCYCD=20ns, max 50MHz, 60fps */
243 .hfp = 50, /* no spec, "don't care" values */
244 .hbp = 50,
245 .hsw = 50,
[all …]
/openbmc/u-boot/drivers/spi/
H A Drk_spi.h123 * We limit the maximum bitrate to 50MBit/s (50MHz) due to an assumed
126 * "sclk_out: spi master internal logic in rk3x can support 50Mhz"
/openbmc/u-boot/board/xes/common/
H A Dfsl_8xxx_clk.c10 * Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config
33 * Return DDR input clock - synchronous with SYSCLK or 66 MHz
/openbmc/linux/Documentation/devicetree/bindings/net/
H A Dmicrel.txt23 - micrel,rmii-reference-clock-select-25-mhz: RMII Reference Clock Select
24 bit selects 25 MHz mode
26 Setting the RMII Reference Clock Select bit enables 25 MHz rather
27 than 50 MHz clock mode.
/openbmc/u-boot/arch/arm/mach-omap2/omap4/
H A Demif.c22 /* Base AC Timing values specified by JESD209-2 for 400MHz operation */
43 .tFAW = 50
46 /* Base AC Timing values specified by JESD209-2 for 200 MHz operation */
67 .tFAW = 50

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