126 	/* Set APLL to 1000MHz */  in board_clock_init()
149 	 * Set dividers for MOUTcore = 1000 MHz  in board_clock_init()
150 	 * coreout =      MOUT / (ratio + 1) = 1000 MHz (0)  in board_clock_init()
151 	 * corem0 =     armclk / (ratio + 1) = 333 MHz (2)  in board_clock_init()
152 	 * corem1 =     armclk / (ratio + 1) = 166 MHz (5)  in board_clock_init()
153 	 * periph =     armclk / (ratio + 1) = 1000 MHz (0)  in board_clock_init()
154 	 * atbout =       MOUT / (ratio + 1) = 200 MHz (4)  in board_clock_init()
155 	 * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1)  in board_clock_init()
156 	 * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0)  in board_clock_init()
157 	 * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk)  in board_clock_init()
170 	 * For MOUThpm = 1000 MHz (MOUTapll)  in board_clock_init()
210 	/* Set MPLL to 800MHz */  in board_clock_init()
235 	 * MOUTdmc = 800 MHz  in board_clock_init()
236 	 * MOUTdphy = 800 MHz  in board_clock_init()
259 	 * MOUTg2d = 800 MHz  in board_clock_init()
260 	 * MOUTc2c = 800 Mhz  in board_clock_init()
261 	 * MOUTpwi = 108 MHz  in board_clock_init()
297 	 * For MOUTuart0-4: 800MHz  in board_clock_init()
313 	 * For MOUTmmc0-3 = 800 MHz (MPLL)  in board_clock_init()
316 	 * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1)  in board_clock_init()
318 	 * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1)  in board_clock_init()
333 	 * For MOUTmmc0-3 = 800 MHz (MPLL)  in board_clock_init()
336 	 * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1)  in board_clock_init()
338 	 * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1)  in board_clock_init()
352 	 * For MOUTmmc4 = 800 MHz (MPLL)  in board_clock_init()
480 	 * The Odroid Us have reference clock at 24 MHz (00 entry from secondary  in set_usb3503_ref_clk()
481 	 * table) and Odroid Xs have it at 26 MHz (01 entry from primary table).  in set_usb3503_ref_clk()